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Observer
Observer
3,863 Views
Registered: ‎09-21-2011

Empty Formality SVF output from Netgen

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Whenever I run Netgen on a map output netlist from ISE, the resultant SVF file is always just template, no content:

#################################################
#
# Product: Netgen
# Vendor: Xilinx
# Target Tool: formality
# Filename: top
# Timestamp: Thu Feb 02 11:56:52 2012
# Version: O.61xd
#
#################################################
#--No constant registers found --
#################################################

 

Now, I know that the design contains constant registers because synthesis spits out dozens of messages about constant registers being optimized.  The netgen batch script I run is:

 

@echo on

REM Setup the Xilinx Environment
call C:\Xilinx\13.2\ISE_DS\settings64.bat

REM Execute Netgen
netgen -ecn formality -ngm top_map.ngm -w top_map.ncd top_ncd_ecn.v

 

 

I have tried this same process on dozens of designs, some very simple and some very complex (processors).  Running the equivalent design through Synopsys Design Compiler generally generates dozens-hundreds of optimization hints in the SVF file, so it is definitely not the case that the design is not optimizable.  The SVF file is always empty and that makes equivalence checking more difficult and involved.

 

Qs:

  1. Why is this file always blank? 
  2. What optimization hints is Netgen capable of reporting via the SVF?
  3. What do I need to do to get SVF content output?
  4. Why is the SVF file only generatable when inputting a map netlist instead of a translate netlist?  Most of the optimizations the SVF contains should have been performed during synthesis anyway...

 

Thanks,

JoRyTe

 

 

 

 

 

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Highlighted
Observer
Observer
4,463 Views
Registered: ‎09-21-2011

I opened up a webcase and got an answer from an engineer.  He wasn't sure, but did some experimenting, research, and communication with the tool designers and discovered only constant register hints are reported by Xilinx in the SVF file and only one scenario that produces a constant register SVF entry:

 

In order for a this to happen, the input value needs to have a constant value of 1, and it needs to be a flip flop primitive such as an FDSE. I have included an instantiation example below where this register is getting a constant value of '1'.

 

parameter d = 1'b1; 

 

   FDSE #(

      .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)

   ) FDSE_inst (

      .Q(Q),      // 1-bit Data output

      .C(clk),      // 1-bit Clock input

      .CE(ce),    // 1-bit Clock enable input

      .S(s),      // 1-bit Synchronous set input

      .D(d)       // 1-bit Data input

   );

 

The report looks like the following:

#################################################

#

# Product: Netgen

# Vendor: Xilinx

# Target Tool: formality

# Filename: top

# Timestamp: Thu Apr 05 18:09:27 2012

# Version: O.87xd

#

#################################################

Operation : reg_constant

Register instance : top/FDSE_inst

Constant value : 1

#################################################

 

 

A request has been placed for Xilinx to support the full gamut of SVF optimization hints, as other tools do, and not just specific constant registers.

 

 

JoRyTe

 

 

 

 

 

 

 

 

 

 

 

View solution in original post

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1 Reply
Highlighted
Observer
Observer
4,464 Views
Registered: ‎09-21-2011

I opened up a webcase and got an answer from an engineer.  He wasn't sure, but did some experimenting, research, and communication with the tool designers and discovered only constant register hints are reported by Xilinx in the SVF file and only one scenario that produces a constant register SVF entry:

 

In order for a this to happen, the input value needs to have a constant value of 1, and it needs to be a flip flop primitive such as an FDSE. I have included an instantiation example below where this register is getting a constant value of '1'.

 

parameter d = 1'b1; 

 

   FDSE #(

      .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)

   ) FDSE_inst (

      .Q(Q),      // 1-bit Data output

      .C(clk),      // 1-bit Clock input

      .CE(ce),    // 1-bit Clock enable input

      .S(s),      // 1-bit Synchronous set input

      .D(d)       // 1-bit Data input

   );

 

The report looks like the following:

#################################################

#

# Product: Netgen

# Vendor: Xilinx

# Target Tool: formality

# Filename: top

# Timestamp: Thu Apr 05 18:09:27 2012

# Version: O.87xd

#

#################################################

Operation : reg_constant

Register instance : top/FDSE_inst

Constant value : 1

#################################################

 

 

A request has been placed for Xilinx to support the full gamut of SVF optimization hints, as other tools do, and not just specific constant registers.

 

 

JoRyTe

 

 

 

 

 

 

 

 

 

 

 

View solution in original post

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