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pranav_vaidya
Newbie
Newbie
8,383 Views
Registered: ‎11-13-2009

Error Creating TBW file - ISE 9.2i

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Hello everyone,

 

This is the first time I am posting to this forum so if I have misplaced my post, I apologize and in that case I would appreciate your input on where I can post this question.

 

 

The problem:

Whenever I try to add a Waveform testbench to a project, ISE 9.2i tells me that -> "Started : "Creating Tbw file"" and nothing happens. No resulting files are created anywhere. ISE just sits there doing nothing.

 

The setup:

ISE 9.2.04i running on  Fedora Core 9 - I cannot use any other ISE version because of some other dependencies that are outside my control.

 

Things that I have tried already:

I tried to see what might be happening by setting the following environment variables

XIL_PROJNAV_FLOW_DEBUG_LEVEL=12
XIL_PROJNAV_OUTPUT_LOG=$HOME/xil.log


Whenever, I add a new waveform test bench to the project I get the following debug messages

Started : "Creating Tbw file".
DEBUG (dpm_bencherCreateTbw): _ParserDuType is Architecture; _AssociatedModule is XXX; _ArchName is RTL
DEBUG (dpm_bencherCreateTbw): _AssociatedFile is /home/test/hdlworkspace/XXX/XXX.vhd
DEBUG (dpm_bencherCreateTbw): ProjectDir is /home/test/hdlworkspace/XXX

DEBUG (dpm_bencherCreateTbw): _Ifmt is vhdl
DEBUG (_PopulatePostAbstractSimulationView): Run Transform "TBIND_AbstractToPostAbstractSimulation_virtex5::TRAN_copyAbstractToPostAbstractSimulation"
DEBUG (dpm_chTransformExecute): TBIND_AbstractToPostAbstractSimulation_virtex5::TRAN_copyAbstractToPostAbstractSimulation with flow proc _copyDUsToOutputView
DEBUG (_PopulatePostAbstractSimulationView): Run Transform "TBIND_AbstractToPostAbstractSimulation_virtex5::TRAN_convertToHdl"
DEBUG (dpm_chCompositeTransformExecute): TransformInputSet.Size is 0
ERROR (_GetDuByNameInSet): No Du found that matches Entity name "XXX" and Parser DU type "Architecture"

 

I also tried creating the project from scratch but nothing different happens.

 

Anybody have any idea why this is happening ?

 

Thank in advance,

Pranav

 

 

 

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pranav_vaidya
Newbie
Newbie
10,164 Views
Registered: ‎11-13-2009

Hello Eddie,


Thank you for your reply. I did try your solution for the ISE examples and I was able to create a test bench waveform for the stopwatch example project. 

 

I just wanted to add some more observations to when this error manifests itself.  When the project gets stuck with this error, I am usually left with no option but to recreate the project again. Here again, sometimes this approach resolves the issue and sometimes it doesnt. Since it works sometimes after I recreate the project, I am kind of hesitant to think along the lines that this might have something to OS support. Another interesting observation is that I get this error when I use a generic top-level module that has generic 2-D inputs.

 

For example, the project that I am talking about has the following top level module declaration.

 

ENTITY  some_entity IS

GENERIC (NUM_INPUTS : NATURAL := 8;

                  DATA_WIDTH : NATURAL := 64

                  )

PORT (

                       -- OTHER IP/OPS

                           P_INPORT : IN STD_LOGIC_2DVECTOR(NUM_INPUTS - 1 DOWNTO 0, DATA_WIDTH - 1 DOWNTO 0);

           );

END some_entity;

 

and I have defined STD_LOGIC_2DVECTOR in one of my packages to be TYPE  STD_LOGIC_2DVECTOR IS ARRAY (INTEGER RANGE <>, INTEGER RANGE <>) OF STD_LOGIC;

 

Do you think it might have something to do with the generics thats causing this issue?

Nevertheless, the good thing I can report now is that yesterday night I recreated the entire project from scratch and this time everything worked smoothly. 

 

Thanks again,

Pranav

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6 Replies
edv
Xilinx Employee
Xilinx Employee
8,356 Views
Registered: ‎08-15-2007

Pranav,

 

Are you able to create a testbench waveform using one of the ISE examples (File --> Open Example)?  If not, this may point to a problem when running the tools on FC9 as this OS is not a supported OS.

 

 

Eddie
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pranav_vaidya
Newbie
Newbie
10,165 Views
Registered: ‎11-13-2009

Hello Eddie,


Thank you for your reply. I did try your solution for the ISE examples and I was able to create a test bench waveform for the stopwatch example project. 

 

I just wanted to add some more observations to when this error manifests itself.  When the project gets stuck with this error, I am usually left with no option but to recreate the project again. Here again, sometimes this approach resolves the issue and sometimes it doesnt. Since it works sometimes after I recreate the project, I am kind of hesitant to think along the lines that this might have something to OS support. Another interesting observation is that I get this error when I use a generic top-level module that has generic 2-D inputs.

 

For example, the project that I am talking about has the following top level module declaration.

 

ENTITY  some_entity IS

GENERIC (NUM_INPUTS : NATURAL := 8;

                  DATA_WIDTH : NATURAL := 64

                  )

PORT (

                       -- OTHER IP/OPS

                           P_INPORT : IN STD_LOGIC_2DVECTOR(NUM_INPUTS - 1 DOWNTO 0, DATA_WIDTH - 1 DOWNTO 0);

           );

END some_entity;

 

and I have defined STD_LOGIC_2DVECTOR in one of my packages to be TYPE  STD_LOGIC_2DVECTOR IS ARRAY (INTEGER RANGE <>, INTEGER RANGE <>) OF STD_LOGIC;

 

Do you think it might have something to do with the generics thats causing this issue?

Nevertheless, the good thing I can report now is that yesterday night I recreated the entire project from scratch and this time everything worked smoothly. 

 

Thanks again,

Pranav

View solution in original post

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edv
Xilinx Employee
Xilinx Employee
8,333 Views
Registered: ‎08-15-2007

Pranav,

 

Thanks for the feedback.  I can't tell for sure whether this was your root cause as, as you state, rebuilding the project resolved the error.  The problems you may have encountered may have been due to a project corruption issue.

 

 

Eddie
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wbrysrmd
Newbie
Newbie
7,955 Views
Registered: ‎03-03-2010

I am using ISE 10.1.3 and experienced the same problem with exact the same behavior.

message  shows up

Started : "Creating Tbw file".

 

then nothing: file is not created

I was using the same program with the same VHDL file yesterday without problems: today it stopped working.

 

Looks like it is a serious, reappearing problem: I have not changed the VHDL source file

 

I have no idea what to do?

I tried to recreate the project but it did not help.

 

Best regards

WieB 

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giangy
Newbie
Newbie
6,931 Views
Registered: ‎01-22-2011

Hi, I've the same problem with test bench waveform....i've ISE 8.1 xilinx tool and when i start a simulation...i see in the console window: Started : "Creating Tbw file" but it does not happen anything....what could i do?? Thanks a lot

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Anonymous
Not applicable
6,690 Views

Hi, I am having the same problem with ISE 10.1.03 (nt). Help would be greatly appreciated... Cheers, Linus

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