hi guys!
I am using ISE v10.1 to implement the FPGA designs.
I write a simple small program in VHDL to implement 'ADD' operation, the folowing:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADDER is
port(
a : in signed(3 downto 0);
b : in signed(3 downto 0);
c : out signed(4 downto 0) );
end ADDER;
architecture Behavioral of ADDER is
begin
c <= a+b;
end Behavioral;
But i can't simulate it. when I simulate ISE generate the errors:
please help me to explain that error (why? and how correct it?). Thank you very much!
all my project attach below.
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