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Observer
Observer
5,182 Views
Registered: ‎12-15-2011

Error in simulation

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hi guys!

I am using ISE v10.1 to implement the FPGA designs.

I write a simple small program in VHDL to implement 'ADD' operation, the folowing:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADDER is

    port(
            a : in signed(3 downto 0);
            b : in signed(3 downto 0);
            c : out signed(4 downto 0) );
    
end ADDER;

architecture Behavioral of ADDER is

begin
    c <= a+b;

end Behavioral;

But i can't simulate it. when I simulate ISE generate the errors:

please help me to explain that error (why? and how correct it?). Thank you very much!

all my project attach below.

I'm Hung
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Observer
Observer
6,548 Views
Registered: ‎12-15-2011
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6 Replies
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Teacher
Teacher
5,175 Views
Registered: ‎08-14-2007

Hi,

besides the fact that you should use numeric_std package instead of  STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED this seems to be a problem of your machine or installation. The tool just crashed, and that can have lots of causes.

 

Also you mentioned to be using ISE 10.x. What simulator are you using? ISIM? That was very fresh and buggy at that time.

Maybe you should consider to use an actual version of ISE/ISIM.

 

Have a nice simulation

  Eilert

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Observer
Observer
5,165 Views
Registered: ‎12-15-2011
thank you eiler!
I use ISE simulator.
can everyone explain clearly to me for it?
I'm Hung
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Moderator
Moderator
5,164 Views
Registered: ‎04-17-2011
Hi Hung,
I agree with eiler. 10.x is really an older version of tool. I ran your design in 13.1 ISE Simulator and it ran fine but I couldn't find any testbench for your module in it. Have you written one? If not try creating a testbench and provide stimulus for a and b and run it in ISIM. The code looks fine.
Regards,
Debraj
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Observer
Observer
5,157 Views
Registered: ‎12-15-2011

Thank debrajr!

I really wrote testbench and do it again several time.

I will retry with respect to you.

I'm Hung
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Observer
Observer
6,549 Views
Registered: ‎12-15-2011
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Moderator
Moderator
5,112 Views
Registered: ‎10-04-2011

Hello,

 

This issue was resolved in service pack 2 of 10.1. Here is an answer record describing a similar issue.:

 

http://www.xilinx.com/support/answers/31079.htm

 

Hope this helps ...

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