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Explorer
Explorer
1,756 Views
Registered: ‎04-12-2012

Error loading design with XPM FIFO

Hello,

 

While trying to simulate a design in Modesim 10.6 - I got an error that mentions: "unresolved reference to glbl".

This is the print-out I got when loading the design (while trying to load it) -

 

# Loading xpm.xpm_fifo_reg_vec
# ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic/wrst_rd_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 1113
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic/rrst_wr_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 1113
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/gen_cdc_pntr/wr_pntr_cdc_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 377
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/gen_cdc_pntr/wr_pntr_cdc_dc_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 377
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/gen_cdc_pntr/rd_pntr_cdc_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 377
# ** Error: (vsim-3043) Unresolved reference to 'glbl'.
#    Time: 0 ns  Iteration: 0  Instance: /tb_fifo/fifo_to_tb_fifo/generate_mode_name_vendor/generate_xpm_asynchronous_fifo/generate_xpm_fwft_asynchronous_fifo/xpm_fifo_async_to_fifo/gnuram_async_fifo/xpm_fifo_base_inst/gen_cdc_pntr/rd_pntr_cdc_dc_inst File: C:/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv Line: 377
# Error loading design
# End time: 19:15:44 on Feb 26,2018, Elapsed time: 0:00:00
# Errors: 6, Warnings: 1
 
Note:
I used Vivado 2017.4 to compile the simulation libraries - which was successful.
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7 Replies
Scholar jmcclusk
Scholar
1,746 Views
Registered: ‎02-24-2014

Re: Error loading design with XPM FIFO

Try including the global reset module at c:\Xilinx\Vivado\2017.4\data\verilog\src\glbl.v

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,719 Views
Registered: ‎05-31-2017

Re: Error loading design with XPM FIFO

Hi @shaikon,

 

Have you compiled the glbl.v file ? Please check this AR#1078 on how to simulate with Modelsim.

 

Thanks & Regards,
A.Shameer

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Explorer
Explorer
1,706 Views
Registered: ‎04-12-2012

Re: Error loading design with XPM FIFO

1. Added glbl.v to project.

2. Compiled everything.

 

Problem wasn't solved. I still get the error.

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Highlighted
Contributor
Contributor
1,291 Views
Registered: ‎09-02-2008

Re: Error loading design with XPM FIFO

I am running into this same issue.  I upgraded to Vivado 2018.2 as well to see if it was fixed.  

 

Compiling glbl.v does not appear to fix this unless I'm doing that incorrectly.

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Xilinx Employee
Xilinx Employee
1,280 Views
Registered: ‎07-16-2008

回复: Error loading design with XPM FIFO

Apart from compiling the glbl.v, did you also load it along with the top level?

e.g.

vsim -L xxx -L xxx work.tb work.glbl

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Contributor
Contributor
1,269 Views
Registered: ‎09-02-2008

回复: Error loading design with XPM FIFO

Yes I tried that yesterday.

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Contributor
Contributor
1,266 Views
Registered: ‎09-02-2008

回复: Error loading design with XPM FIFO

I messed around with it a little more and this worked.  I'm used to opening modelsim and starting the testbench within the gui.  Thanks!

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