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adam_mira
Participant
Participant
308 Views
Registered: ‎01-13-2020

Error loading simulation - " Fatal Error size mismatch "

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Hi,

I am trying to simulate the DDS IP. I am using VIVADO 2017.4 to run the simulation in QuestaSim.

I am getting the following error message:

"Failure: ERROR: phase tdata size mismatch. Expected 32 Got 16"

 I configured the phase tdata to be 16 bits in the IP configurator and it also as displayed in the .vho instantiation template.

The DDS IP files are protected and can't be viewed or modified. 

Any ideas on how to fix this problem?

Thank you!

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ansarimo
Xilinx Employee
Xilinx Employee
154 Views
Registered: ‎12-04-2019

Hi @adam_mira 

I suspect in 2020.2 it is working.

Please let us know if you need any further assistance or else close this thread by accepting it as a solution.

Hope this helps.

 

Thanks and Regards,
Ansari Hunen
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1 Reply
ansarimo
Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎12-04-2019

Hi @adam_mira 

I suspect in 2020.2 it is working.

Please let us know if you need any further assistance or else close this thread by accepting it as a solution.

Hope this helps.

 

Thanks and Regards,
Ansari Hunen
------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as a solution.
------------------------------------------------------------------------

View solution in original post