03-30-2019 09:20 AM
I am not getting simulation of a VHDL program but Its RTL schematic can be generated.It is showing error in XST simulator.Please anyone tell me the solution as soon as possible.
04-01-2019 03:50 AM
Hi @mani_905 ,
Can you please share the error message which you have come across while simulating in ISIM? Are you using ISE 14.7 and on which OS?
04-03-2019 08:36 PM
HI @mani_905 ,
You can try to simulate individual files present in the hierarchy to find which file contains the code due to which ISE is giving the error.
As its a very older version tool, you can also give a try migrating to ISE 14.7 or latest VIvado version (2018.3).