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Visitor
Visitor
6,016 Views
Registered: ‎09-23-2009

Error simulating EDK design with MCB memory controller

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Hi Everyone

     I am having problem simulating an EDK design using ModelSim 6.5 SE. It seems that everytime when I invoke the simulator, I always get the below error message:

 

** Error: C:/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims/MCB.v(1647): Module 'B_MCB' is not defined.
# ** Error: C:/Xilinx/12.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_00_a/hdl/vhdl/plbv46_pim_wrapper.vhd(179): Vopt Compiler exiting

 

Indeed when I look at MCB.v file, it will instantiate B_MCB module but I can't locate the B_MCB anywhere. Does anybody else have any clue of how to solve this problem. I am also using one of the port as VFBC.

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Xilinx Employee
Xilinx Employee
7,319 Views
Registered: ‎09-14-2007

Re: Error simulating EDK design with MCB memory controller

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ii,

 

The MCB block is a secureip. Please ensure that you have -L secureip in your vsim script.

 

For more information on secureip, see here -

 

http://www.xilinx.com/support/answers/32936.htm

 

Thanks

Duth

 

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Xilinx Employee
Xilinx Employee
7,320 Views
Registered: ‎09-14-2007

Re: Error simulating EDK design with MCB memory controller

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ii,

 

The MCB block is a secureip. Please ensure that you have -L secureip in your vsim script.

 

For more information on secureip, see here -

 

http://www.xilinx.com/support/answers/32936.htm

 

Thanks

Duth

 

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Contributor
Contributor
4,938 Views
Registered: ‎12-16-2009

Re: Error simulating EDK design with MCB memory controller

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Hi,

 

  I'm having the same problem but the solution you suggested does not seem to work. I am using:

 

vsim -novopt -t ps -L secureip -L xilinxcorelib_ver -L xilinxcorelib -L unisims_ver +notimingchecks system_tb glbl

 

the secureip has been compiled, it is mapped:

 

vmap secureip "C:/Xilinx/13.3_NEW_LIB/secureip/"

 

All else seems OK but I still get:

 

# Loading mpmc_v6_05_a.mcb_raw_wrapper
# Loading unisims_ver.MCB
# ** Error: (vsim-3033) C:/Xilinx/13.3/ISE_DS/ISE/verilog/src/unisims/MCB.v(1648): Instantiation of 'B_MCB' failed. The design unit was not found.
#         Region: /system_tb/dut/DDR3_SDRAM_1/DDR3_SDRAM_1/mpmc_core_0/gen_spartan6_mcb/s6_phy_top_if/mpmc_mcb_raw_wrapper_0/samc_0
#         Searched libraries:
#             C:\Xilinx\13.3_NEW_LIB\secureip
#             C:\Xilinx\13.3_NEW_LIB\xilinxcorelib_ver
#             C:\Xilinx\13.3_NEW_LIB\xilinxcorelib
#             C:\Xilinx\13.3_NEW_LIB\unisims_ver
#             C:\Xilinx\13.3_NEW_LIB\unisims_ver

 

Please help if you can.

 

Thanks,

Jacob

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Xilinx Employee
Xilinx Employee
4,932 Views
Registered: ‎07-16-2008

Re: Error simulating EDK design with MCB memory controller

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How did you compile the Xilinx simulation libraries? Please make sure all secureip modules have been successfully compiled.

 

If you used 'compxlib', you can check compxlib.log.

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Newbie
Newbie
4,880 Views
Registered: ‎07-06-2012

Re: Error simulating EDK design with MCB memory controller

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Hi, I also meet the question that the "B_MCB" can't be found.

And I check the compxlib log, there are some errors when compile the securip library. 

I re-complie the securip library, but it doesn't work.

Can you tell me how to solve the problem?

 

-- Compiling module PCIE_A1_WRAP
###### D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(2): `pragma protect version = 1
** Error: D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(2): Missing '`pragma protect ????_block encoding'
** Error: D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(2): Pragma protect keyword expected
###### D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(4): `pragma protect author = "Xilinx" , author_info = "mcb.008"
** Error: D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(4): A key_method must be specified.
** Error: D:\Xilinx\13.3\ISE_DS\ISE\secureip\mti\mcb_mti\mcb_001.vp(4): near ",": syntax error, unexpected ',', expecting "class"

...................................

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Xilinx Employee
Xilinx Employee
4,876 Views
Registered: ‎07-16-2008

Re: Error simulating EDK design with MCB memory controller

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From the log file, you're using Modelsim 6.5c, which is not compatible with ISE 13.x. Please refer to the following documentation, "Xilinx Supported Simulators and Operating Systems" under Chapter 6.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/sim.pdf

 

You need to upgrade to 6.6d and above.

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