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Visitor
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Registered: ‎11-02-2017

Error when compiling secureip for Active HDL

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Hello,

 

I was compiling the Vivado simulation libraries for Active HDL using the following command:

 

compile_simlib -directory compiled_simlibs -force -simulator active_hdl -32bit -verbose

 

 

And I got the following error for secureip:

compile_simlib[exe]: The command line 'C:\Aldec\Active-HDL-10.4\bin/vlib C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip' returned exit code '0'.
--> Compiling 'verilog.secureip' library...
    > Source Library = 'C:\Xilinx\Vivado\2017.2\data/secureip'
    > Compiled Path  = 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip'
Executing cmd 'C:\Aldec\Active-HDL-10.4\bin/vlog -v2k5 -work secureip -f C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.cmf' with output 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.log' (Thu Nov  2 11:07:25 2017)...
compile_simlib[exe]: The command line 'C:\Aldec\Active-HDL-10.4\bin/vlog -v2k5 -work secureip -f C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.cmf' returned exit code '0'.
Executing cmd 'C:\Aldec\Active-HDL-10.4\bin/vlog -v2k5 -sv -work secureip -f C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.systemverilog.secureip.secureip.nt64.cmf' with output 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.log' (Thu Nov  2 11:07:25 2017)...
ERROR: [Common 17-180] Spawn failed: No such file or directory
compile_simlib[exe]: The command line 'C:\Aldec\Active-HDL-10.4\bin/vlog -v2k5 -sv -work secureip -f C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.systemverilog.secureip.secureip.nt64.cmf' returned exit code '-1'.
==============================================================================
BEGIN_COMPILATION_MESSAGES(active_hdl:verilog:secureip)
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE_SP VCP2113 "Module \$root found in current working library."
ERROR VCP1230 "Error in encrypted code."
FAILURE "Compile failure 1 Errors 0 Warnings  Analysis time: 0[s]."

END_COMPILATION_MESSAGES(active_hdl:verilog:secureip)
==============================================================================
    > Log File       = 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.log'
Reading the cxl log file - 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.log' for warnings...
Generating the cxl result file - 'C:\Aldec\Active-HDL-10.4\vlib\compiled_simlibs/secureip/.cxl.verilog.secureip.secureip.nt64.rpt' ...
compile_simlib[verilog.secureip]: 1 error(s), 0 warning(s), 16.67 % complete

I couldn't understand the error message. Can anyone help me with this issue? I am using Vivado 2017.2 and Active HDL 10.4 (plus edition).

 

Thank you!

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Xilinx Employee
Xilinx Employee
2,655 Views
Registered: ‎07-16-2008

Re: Error when compiling secureip for Active HDL

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This is a compile_simlib issue. Please refer to the following AR:

https://www.xilinx.com/support/answers/69252.html

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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Error when compiling secureip for Active HDL

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Hi @yuboli_sel

 

Can run the command specifying simulator executable path as shown below?

compile_simlib -directory C:/Xilinx/Vivado/2017.2/SimLib -simulator active_hdl -simulator_exec_path <simulator_executable_path>/bin

 

Regards

Rohit

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Regards
Rohit
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Visitor
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Registered: ‎11-02-2017

Re: Error when compiling secureip for Active HDL

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Hi @thakurr,

 

Thank you for the reply. I tried your command and got a different error:

 

secureip = C:\Xilinx\Vivado\2017.2\SimLib\secureip\secureip.lib

--> Compiling 'verilog.secureip' library...
    > Source Library = 'C:\Xilinx\Vivado\2017.2\data/secureip'
    > Compiled Path  = 'C:\Xilinx\Vivado\2017.2\SimLib/secureip'
ERROR: [Common 17-180] Spawn failed: Broken pipe
==============================================================================
BEGIN_COMPILATION_MESSAGES(active_hdl:verilog:secureip)
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE_SP VCP2113 "Module \$root found in current working library."
ERROR VCP1230 "Error in encrypted code."
FAILURE "Compile failure 1 Errors 0 Warnings  Analysis time: 1[s]."

END_COMPILATION_MESSAGES(active_hdl:verilog:secureip)
==============================================================================
    > Log File       = 'C:\Xilinx\Vivado\2017.2\SimLib/secureip/.cxl.verilog.secureip.secureip.nt64.log'
compile_simlib[verilog.secureip]: 1 error(s), 0 warning(s), 16.67 % complete

Thanks,

Yubo

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Xilinx Employee
Xilinx Employee
2,656 Views
Registered: ‎07-16-2008

Re: Error when compiling secureip for Active HDL

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This is a compile_simlib issue. Please refer to the following AR:

https://www.xilinx.com/support/answers/69252.html

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Don't forget to reply, kudo, and accept as solution.
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View solution in original post

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Visitor
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Registered: ‎11-02-2017

Re: Error when compiling secureip for Active HDL

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That works. Thanks!

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