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Visitor
Visitor
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Registered: ‎11-02-2017

Error when generating programming file

module CounterMux(clk, reset, sel, LED);

// Inputs
input clk, reset;
input [1:0] sel;


//output
output reg [7:0] LED;

reg [31:0]out1;
reg [31:0]Q;

reg [7:0] d1,d2,d3,d4;

Bit32 counter_inst(clk, reset, out1, Q);

/*
d1 <= Q[7:0];
d2 <= out1[15:8];
d3 <= out1[23:16];
d4 <= out1[31:24];
*/
always @*
begin
case(sel)
2'b00 : LED <= out1[7:0];
2'b01 : LED <= out1[15:8];
2'b10 : LED <= out1[23:16];
2'b11 : LED <= out1[31:24];
default : LED <=0;
endcase
end
endmodule

 

ERROR CODE:  Line 16: Target <out1> of concurrent assignment or output port connection should be a net type.

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2 Replies
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Moderator
Moderator
760 Views
Registered: ‎04-12-2017

Re: Error when generating programming file

Hello @cotton117,

 

 

I think you are trying to implement some special kind of counter example here.

 

Please try to write complete sensitivity list and use If-Else looping rather than case statement.

The '*' can be used as short of all inputs only if logic inside always block is purely combinational.

 

Hope this resolves your query.

Thank you.

 

 

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Scholar
Scholar
708 Views
Registered: ‎02-01-2013

Re: Error when generating programming file

@cotton117 :

 

Your coding/style needs a lot of work, too, but this is your immediate problem:

 

cotton-1.jpg

 

-Joe G.

 

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