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Visitor salisen
Visitor
610 Views
Registered: ‎06-16-2015

Error when simulating Xilinx block memory based FIFO in testbed

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I'm currently grappling with an odd but fatal issue with the Vivado Simulator running in Vivado 2018.1 in GUI mode.

 

I have a testbench that includes a Xilinx Block RAM based FIFO generated and instantiated using the Xilinx FIFO Generator IP block.

 

Unfortunately I am struggling to get the Vivado Simulator to successfully run behavioural simulation with this FIFO in place in the testbench.  I am getting the following error, which is causing simulation to fail:

 

ERROR: [VRFC 10-149] 'fifo_generator_v13_2_1_pkg' is not compiled in library fifo_generator_v13_2_1 [C:/Users/karic/Dropbox/PhD/Share_w_Kari/FPGA_Projects/phase_cache_locking_time/phase_cache.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd:3882]
INFO: [VRFC 10-307] analyzing entity shft_wrapper
ERROR: [VRFC 10-1504] unit shft_wrapper ignored due to previous errors [C:/Users/karic/Dropbox/PhD/Share_w_Kari/FPGA_Projects/phase_cache_locking_time/phase_cache.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd:3887]

 

I have found a couple of references to similar errors online but they appear to correspond to compiling libraries for external simulation tools such as ModelSIM and QuestaSIM.

 

I have tried deleting and regenerating the FIFO, without success.  I have also tried experimenting with the compilation order, again without success.

 

I am at a complete loss as to how to solve this issue.  Does anyone have any ideas?

 

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Moderator
Moderator
753 Views
Registered: ‎04-24-2013

Re: Error when simulating Xilinx block memory based FIFO in testbed

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Hi @salisen,

 

The fifo generator version 13.2 rev 1 is provided with Vivado 2017.4, 2018.2 is supplied with Rev 2 so this may be why you are seeing this issue. If you run Report IP Status and upgrade the IP does this help?

 

You could also try running reset_project in the tcl console.

 

If neither of these help then you could try deleting the project.sim directory. This will be regenerated when you run simulation again.

 

Best Regards
Aidan

 

 

 

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2 Replies
Moderator
Moderator
754 Views
Registered: ‎04-24-2013

Re: Error when simulating Xilinx block memory based FIFO in testbed

Jump to solution

Hi @salisen,

 

The fifo generator version 13.2 rev 1 is provided with Vivado 2017.4, 2018.2 is supplied with Rev 2 so this may be why you are seeing this issue. If you run Report IP Status and upgrade the IP does this help?

 

You could also try running reset_project in the tcl console.

 

If neither of these help then you could try deleting the project.sim directory. This will be regenerated when you run simulation again.

 

Best Regards
Aidan

 

 

 

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Visitor salisen
Visitor
549 Views
Registered: ‎06-16-2015

Re: Error when simulating Xilinx block memory based FIFO in testbed

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No IP upgrade was required as per report_ip_status (the FIFO IP was already compiled at version 13.2 Rev 2).

 

However running reset_project and then deleting the project.sim directory worked (not sure which step did the trick but it was one of the two).

 

I think the issue was that the simulation was stale - it was I presume expecting Version 13.2 Rev 1 of the FIFO judging by the error message, and then not finding it since Version 13.2 Rev 2 was present in the project.

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