09-11-2015 10:14 AM
I have a project in Vivado 2014.4 and am simulating in QuestaSim 10.3c. When I go to simulate, I get the following error when compiling in QuestaSim:
# ** Error: ...../blank_delay_32x7ram/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vh_rfs.vhd(46): Can't recompile existing unprotected design unit "dist_mem_gen_v8_0" as protected.
Has anyone else seen this error before? I cannot find anything about it. I have already tried recompiling the libraries and that did not work.
09-11-2015 11:14 AM
Have you tried running in Questa 10.3b?
09-11-2015 11:13 PM
It looks like you are not using correct set of IP files for simulation.
You can use the below command in Vivado project to identify the IP files which needs to be used for simulation.
get_files -compile_order sources -used_in simulation -of_objects [get_files <ip_name>.xci]
You can also set the simulator to Questasim (the one you use) in simulation settings and use the below command to generate scripts
You can then use the generated scripts to run simulation in standalone simulator.
09-14-2015 03:47 AM
I will try running that command. I am already currently setting the simulator to Questa/Modelsim in the settings and allowing it to generate a compile script for me, and it is giving me the error. I will try using that command.
09-14-2015 11:00 AM
I tried that command, but it gives the same files to compile as I already was compiling. I am using a script generated by Vivado through the built in simulator with Questa/Modelsim set as the simulator. So that didn't work.
09-14-2015 10:41 PM
Can you attach the script you were using here?
09-15-2015 04:04 AM
The two lines for compiling the IP in the script are as follows:
vcom -work dist_mem_gen_v8_0 "....../blank_delay_32x7ram/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vh_rfs.vhd"
vcom -work xil_defaultlib "....../blank_delay_32x7ram/sim/blank_delay_32x7ram.vhd"
09-15-2015 04:50 AM
I am able to simulate the 2014.4 IP example design succesfully at my end.
Can you check if you have compiled libraries properly?
We have started delivering the non-encrypted behavioral models from Vivado 2015.1. In case if you have access to this version of tool you can give a try.
09-15-2015 05:33 AM
I am pretty sure I am compiling them correctly. I am going to Tools>Compile Simulation Libraries. Within there, I am selecting Questa, VHDL, Kintex-7 (which is the FPGA I am using), and All libraries. Is this correct?
09-15-2015 06:50 AM
Yes, that is correct.
Can you attach the simulation log file here?