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Visitor psmemin1
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Registered: ‎04-09-2019

Error with VHDL integer signal connecting Verilog integer input

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I trying to connect VHDL module's output integer port to signal. And this signal will connect other module. (This module wrote in Verilog). But I encounter this ERROR :

VHDL integer data type not supported for actual signals in component instantiation across language boundaries. Port "fifo4_frame_number" is an integer VHDL signal connected to a Verilog port.

I must also say that i can generate bitstream. there is no problem.

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220 Views
Registered: ‎01-22-2015

Re: Error with VHDL integer signal connecting Verilog integer input

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@psmemin1 

As drjohnsmith says, when instantiating VHDL in Verilog, only the following VHDL data types are supported:  bit, bit_vector, std_logic, std_ulogic, std_logic_vector, std_ulogic_vector.

See chapter 9 of UG901 for details of Vivado mixed language support.

Mark

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: Error with VHDL integer signal connecting Verilog integer input

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it always used to be that verilog and VHDL were only compatable at the bit level,

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_r_mixed_lang_boundary_mapping_rules.htm

It might have changed, but std_logic and std_logic_vector were the limits.

 

( Im old fasioned , and have to work with lots of OLD code, and stil only interface at the bit level )

 

Would be interesting to know if others are now supported.

 

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Visitor psmemin1
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Registered: ‎04-09-2019

Re: Error with VHDL integer signal connecting Verilog integer input

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i read this document.
Generics (Parameters) Mapping
Following VHDL generic types (and their Verilog equivalents) are supported.
integer
real
string
boolean
Note Any other generic type found on mixed language boundary is considered an error.

i think integer types also compatable.
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221 Views
Registered: ‎01-22-2015

Re: Error with VHDL integer signal connecting Verilog integer input

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@psmemin1 

As drjohnsmith says, when instantiating VHDL in Verilog, only the following VHDL data types are supported:  bit, bit_vector, std_logic, std_ulogic, std_logic_vector, std_ulogic_vector.

See chapter 9 of UG901 for details of Vivado mixed language support.

Mark

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: Error with VHDL integer signal connecting Verilog integer input

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Your dead right

 

for generic paramiters, integers are valid

 

bu tyo uare after port paramiters, for which its std_logic and std_logic_vector

 

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