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Visitor
Visitor
110 Views
Registered: ‎06-19-2018

Errors creating simulation sets

I've been noticing strange behavior attempting to create simulation sets for unit tests in Vivado 2019.2. In short, adding/creating files with similar (but not identical) names seems to cause the hierarchy analyzer to choose the wrong file.

Steps to reproduce (defaults for wizards unless described below):

  1. Create a new project, in my case a XC7K410tfbg6767-2, using VHDL language
  2. In the sources hierarchy, select "Add new source"
    1. Select "Add or create simulation source" radio button
    2. In the dialog box, from the "Specify Simulation Set", select "Create Simulation Set"
    3. Call this set "UnitTest_ExecutionEngineSequencer"
    4. Select "Create File", set to VHDL and name it "Test_ExecutionEngineSequencer.vhd"
    5. Do not add/name any port pins.  Note: this step seems to prevent importing the template, we get a blank file.  This is an annoyance, but not the reason for this post
    6. In the file, i create a basic 2-port VHDL entity and architecture.  This content does not appear to be significant, however, it should be valid VHDL w/o syntax errors
    7. Save and close the VHDL file
  3. Now add a second simulation set:
    1. Select "Add new sources" as above, again choosing "add or create simulation source"
    2. Again, from the "Specify simulation set" dropdown, select "Create simulation set", and name it "UnitTest_ExecutionEngine" (note the shortened name)
    3. Again, create a new VHDL file, naming it "Test_ExecutionEngine.vhd"
    4. Add some valid VHDL, but the port specification and entity names can change at will.
    5. Save
  4. Notice that prior to step 3.4 the sources hierarchy has two simulation test sets (plus the default "sim_1" set).  These have the correct names:
    1. UnitTest_ExecutionEngineSequencer
    2. UnitTest_ExecutionEngine
  5. However, the second set create does NOT contain the correct file "Test_ExecutionEngine.vhd".  It seems to scan and find the first file created "Test_ExecutionEngineSequencer.vhd", and use this for BOTH (Screenshot attached)

Observations

  • The correct files are found in the Sources->libraries tab.  This seems to only affect the Sources->hierarchy tab.
  • There does not seem to be a way to override this.  Re-scanning the hierarchy manually does not change the result (although it seems to take a bit longer to wheel-spin at the "updating..." message.
  • The contents of the XPR project file seem correct...the <FileSet> collections contain the correct files in the correct simulation sets.
  • Clearing the Cache directories, JOU and LOG files does not affect the results
  • Changing directories for the project also has no effect...I don't think this is a case of >256 character paths
  • Have not tested this with Verilog

Workarounds

This seems to be a problem of the similarity of the filenames, whose similarity stops after 20 characters.  I could change the names of my testbench files, and the corresponding simulation sets, but this would change my whole V&V test plan, which has already been approved.  Alternatively, I simply not use Vivado for unit testing.

 

Thanks for your help,

Rich

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Visitor
Visitor
60 Views
Registered: ‎06-19-2018

Re: Errors creating simulation sets

UPDATE: This problem seems to be localized to the name of the test set itself, not the files contained therein.

For example, by editing the XPR file directly, I can reproduce the problem with two test sets containing ANY files, by naming them ("Name" attribute in the FileSet XML tag) "UnitTest_ExecutionEngineSequencer" and "UnitTest_ExecutionEngine".

However, when the simulation set name is changed to "UnitTest_ExecutionEngineSequencer" and "UnitTest_Execution_Engine", Vivado works as expected.
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Xilinx Employee
Xilinx Employee
40 Views
Registered: ‎07-16-2008

Re: Errors creating simulation sets

Thank you for the effort on narrowing down the problem. I'll reproduce and submit a CR to dev team.

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