08-18-2019 03:18 PM
Hello, i'm having trouble in one simple code here.
The synthesis and syntax are both ok, but when i create the test bench and run "Simulate Behavioral Model", all the waveforms are with the "U" value.
It's a simple implementation of Petri Net.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity RPetri_seg is Port ( CLOCK : in STD_LOGIC; RESET : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; LED_0 : out STD_LOGIC; LED_1 : out STD_LOGIC; LED_2 : out STD_LOGIC); end RPetri_seg; architecture PETRI_ARQ of RPetri_seg is SIGNAL E: std_logic_vector (3 downto 0); begin process (CLOCK,RESET) begin if RESET = '1' then E <= "0001"; -- marcação inicial elsif CLOCK'EVENT AND CLOCK = '1' THEN E(0) <= (E(0) AND NOT A) OR (E(2) AND (A OR B)) OR E(3); E(1) <= (E(0) AND A) OR (E(1) AND NOT B AND NOT C); E(2) <= (E(1) AND B) OR (E(2) AND NOT (A OR B)); E(3) <= (E(1) AND C); end if; end process; LED_0 <= E(1) OR E(2); LED_1 <= E(2); LED_2 <= E(3); end PETRI_ARQ;
Here is some prints of what i'm talking about:
Why it's happening? How can i fix it?
08-19-2019 04:14 PM
08-18-2019 04:31 PM
08-18-2019 04:49 PM
08-18-2019 05:18 PM
i can upload the entire project and post here.
For now, please show us only the VHDL text file for the testbench - in the same way that you showed us the VHDL text file for entity, RPetri_seg.
08-18-2019 05:34 PM
i think it's the same vhdl code for both test bench and entity, because i didn't create any other vhdl file.
If it is created in the moment i created the Test Bench source, so i dont know where to find it, sorry, i'm a beginner.
08-18-2019 10:33 PM
Try to either apply an initial reset or assign initial value to signal "E".
08-19-2019 04:50 AM
In order to test your component, RPetri_seg, using ISE simulation, you will need to generate the inputs, (CLOCK, RESET, A, B, C), to RPetri_seg. Normally, we provide these inputs by writing a small VHDL component called a testbench. It appears that you are generating these inputs by another (automated?) method, which I don’t recommend. Writing a simple VHDL testbench is described by the following website.
A tutorial for using the ISE simulator, ISIM, is given in Xilinx document UG682.
08-19-2019 04:14 PM