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Observer
Observer
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Registered: ‎02-26-2019

External SRAM implementation and Test bench

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Hi All,

In our project we are using Sparton 6 FPGA with  external 128K X 8 bit CMOS SRAM.

I am new to VHDL coding, i don't know how to write Test bench to this implementation

please share if any related links and code to referer

Could anyone give me suggestions?

Thanks a lot!

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Observer
Observer
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Registered: ‎02-26-2019

Re: External SRAM implementation and Test bench

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476 Views
Registered: ‎06-21-2017

Re: External SRAM implementation and Test bench

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Many commercial RAMs have simulation models available.  Have you searched the manufacturer's for a simulation model?

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Observer
Observer
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Registered: ‎02-26-2019

Re: External SRAM implementation and Test bench

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Hi,

No,We are using Par# LP62S1024BV-70LLIF 128K X 8

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: External SRAM implementation and Test bench

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SRAMs are fairly simple. It shouldnt be hard to create your own model using the datasheet.

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Observer
Observer
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Registered: ‎02-26-2019

Re: External SRAM implementation and Test bench

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Hi,

 

Can you please provide some sample codes or links 

 

Regards,

siva 

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Adventurer
Adventurer
404 Views
Registered: ‎01-27-2008

Re: External SRAM implementation and Test bench

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Hi Sive,

You can probably google around and find some direct examples. Here's one such example for a SRAM and testbench in VHDL.

https://www.fpga4student.com/2017/08/vhdl-code-for-single-port-ram.html

 

You can also pull SRAM that is similar to the one you have to model. Ensure that it's similar in the bus interface and you should be (mostly) good.

For instance, Cypress provides models:  Here's several models:

https://www.cypress.com/search/all?f[0]=meta_type%3Asoftware_tools&f[1]=field_related_products%3A1275&f[2]=software_tools_meta_type%3A580

Have fun,

Jerry

 

 

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Observer
Observer
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Registered: ‎02-26-2019

Re: External SRAM implementation and Test bench

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