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Explorer
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Registered: ‎05-11-2012

FATAL ERROR: Vivado Simulation

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I am attempting to simulate a project in Viavado 2013.2.  The project is mixed language.  When I attempt to run the simulation, I get the following error message:

 

FATAL_ERROR: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

 

This project is the combination of 2 previous projects that each simulated without any issues, but since I have combined the 2 components into 1 project, I can't simulate the project.  

 

I am unable to open a WebCase.  Does anyone have any help that would allow me to get past this issue?  I found this previous forum post about the same error message, but didn't know if there is a better method of determining the cause of the issue that the Trial and Error method of removing components.

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Explorer
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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The error messages posted above for specific files within various Libraries was found to be due to old Library Use statements that were no longer needed in the file.  Once they were removed, the error messages went away.

 

In Vivado 2013.3, my project was able to simulate without any errors.  To determine what file was causing the FATAL ERROR Message to appear, I created a new project in Vivado 2013.2 and slowly started trying to simulate certain portions of the project and adding other modules as the lower modules simulated without error.  In my project, I had a Verilog Module for a specific chip that appeared to be the cause of the FATAL ERROR Message, despite the Verilog module working in ISE 14.5 and PlanAhead 14.5.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: FATAL ERROR: Vivado Simulation

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Hi,

 

Can you please confirm if you have gone through the suggestions from related threads and none of them helped for your case?

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-Simulator-Fatal-Error/td-p/256260

 

http://forums.xilinx.com/t5/Installation-and-Licensing/Fatal-Error-Vivado-2013-2/td-p/356929/page/2

 

 

Regards,

Vanitha.

 

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Explorer
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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Hi Vanitha,

 

The suggestions in the first link are the ones I was referring to in my initial post.  I have not attempted to remove components because the project I am simulating is a custom IP for an XPS project and removing components would essentially prevent the IP from working.

 

The second link is unreleated to my issue because I am not having issues with the license for the software.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: FATAL ERROR: Vivado Simulation

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Hi,

 

Can you share the simulation log file so that one of us may take a look and give you any clues?

 

 

Regards,

Vanitha.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: FATAL ERROR: Vivado Simulation

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Hi,

Try running simulation in 32-bit vivado.

Thanks.
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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Unlike with ISE, I don't see a seperate 32-bit version of Vivado in my Programs.  Could you elaborate on how to try running the simulation in 32-bit Vivado?

 

I will attach the log file shortly for the current simulation run that I am attempting.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: FATAL ERROR: Vivado Simulation

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Hi,

1. Open command prompt
2. Go to <Vivado_installed_directory>\Xilinx\2013.x\ using cd command
3. run settings64.bat
4. Then type "vivado -m32" without quotes

Vivado GUI pops up in 32-bit mode.

Thanks

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Explorer
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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Attached is the Siulation Log.

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Explorer
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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When I open the Vivado GUI in 32-bit mode, as previously described, I still get the same FATAL ERROR when I attempt to run the simulation.

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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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Attached is the Simulation Log from when I attempted to use the 32-bit Vivado GUI

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: FATAL ERROR: Vivado Simulation

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Can you please try in 2013.3 and see if the crash is fixed?

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Explorer
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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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I installed Vivado 2013.3 and then opened my project in the latest software so that the project was converted.  I have one IP (BRAM) in the design that I updated to the latest version.

 

When I attempt to run the simulation, I no longer get the FATAL ERROR message, but rather get the below error messages:

ERROR: [VRFC 10-149] 'proc_common_pkg' is not compiled in library proc_common_v3_00_a [C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd:26]

 

ERROR: [VRFC 10-149] 'ipif_pkg' is not compiled in library proc_common_v3_00_a [C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd:27]

 

ERROR: [VRFC 10-149] 'axi_lite_ipif' is not compiled in library axi_lite_ipif_v1_01_a [C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd:30]

 

ERROR: [VRFC 10-149] 'axi_master_burst' is not compiled in library axi_master_burst_v1_00_a [C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd:33]

 

ERROR: [VRFC 10-1504] unit axi4lite ignored due to previous errors [C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd:45]

 

INFO: [VRFC 10-240] VHDL file C:/projects/SIMS/NAND_Simulation_ISE/hdl/vhdl/AXI4Lite.vhd ignored due to errors

 

I have tried removing these libraries from my project and re-adding them, but I still get these errors.  Attached is the xelab.log file for the simulation run in Vivado 2013.3.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: FATAL ERROR: Vivado Simulation

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Hi,

 

In Libraries tab of Sources Window of Vivado GUI. Are you observing the file proc_common_pkg.vhd under the library "proc_common_v3_00_a"

Similar observe the other files as mentioned in the error.

 

Thanks

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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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I believe that I am observing the proc_common_pkg.vhd file under the "proc_common_v3_00_a" library in the Libraries tab...I will double check this in the AM when I get to work.  

 

If I am infact seeing those files listed in the error message under each respective library in the Libraries Tab, what else could I try to correct these errors?

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Registered: ‎05-11-2012

Re: FATAL ERROR: Vivado Simulation

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The error messages posted above for specific files within various Libraries was found to be due to old Library Use statements that were no longer needed in the file.  Once they were removed, the error messages went away.

 

In Vivado 2013.3, my project was able to simulate without any errors.  To determine what file was causing the FATAL ERROR Message to appear, I created a new project in Vivado 2013.2 and slowly started trying to simulate certain portions of the project and adding other modules as the lower modules simulated without error.  In my project, I had a Verilog Module for a specific chip that appeared to be the cause of the FATAL ERROR Message, despite the Verilog module working in ISE 14.5 and PlanAhead 14.5.

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: FATAL ERROR: Vivado Simulation

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Thanks for sharing the information. This should be a tool bug which has been addressed in 2013.3.

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