FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover.

[sribooshan]

I tried to simulate the testbench for this code given below but I get this error: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. And the simulation never ends.

module d_flip_flop(
    input d,clk,reset,
    output reg q
    );
    always@(posedge clk or negedge reset)
    begin
    if(!reset)
    q<=0;
    else 
    q<=d;
    end
endmodule

The testbench code is:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 08.01.2020 22:51:34
// Design Name: 
// Module Name: d_flip_flop_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module d_flip_flop_tb();
reg d1,clk1,rst;
wire q1;
d_flip_flop uut(.d(d1),.clk(clk1),.reset(rst),.q(q1));
always
begin 
#50 clk1=~clk1;
end
initial 
begin
clk1<=0;
rst<=1; #20;
rst<=0;
d1<=0; #40;
d1<=1; #40;
d1<=0; #40;
d1<=1; #40;
d1<=0; #40;
d1<=1; #40;
rst<=0;
d1<=0; #40;
d1<=1; #40;
end
endmodule

Please help me to solve this problem.

[graces]

I cannot reproduce the failure using the exact RTL code. How did you launch simulation? What is Vivado version?

[sribooshan]

I use Vivado 2019.1.

I launched using Run Behavioral Simulation.

[sribooshan]

The exact message in the Tcl Console is:

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 0 ns Iteration: 0

Please look at the time and iteration.

I tried uninstalling Vivado 2019.1 and installed Vivado 2017.4.

Using Vivado 2017.4, I could simulate this design source directly

`timescale 1ns / 1ps

module basic_gates(
    input a,
    input b,
    output and_out, or_out, xor_out
    );
    assign and_out = a&b;
    assign or_out = a|b;
    assign xor_out = a^b;
endmodule

But when I tried to simulate the below given design using the testbench(given below), I got the above FATAL_ERROR.

`timescale 1ns / 1ps

module encoder(
    input i0,
    input i1,
    input i2,
    input i3,
    input en,
    output y0,
    output y1
    );
    assign y0 = en & i1 & i3;
    assign y1 = en & i2 & i3;
endmodule

The testbench code is

`timescale 1ns / 1ps

module encoder_tb();
reg I0,I1,I2,I3,EN;
wire Y0,Y1;

encoder uut(I0,I1,I2,I3,EN,Y0,Y1);

initial
begin

I0=0;I1=0;I2=0;I3=1;EN=1; #50;
I0=0;I1=0;I2=1;I3=0;EN=1; #50;
I0=0;I1=1;I2=0;I3=0;EN=1; #50;
I0=1;I1=0;I2=0;I3=0;EN=1; #50;
I0=1;I1=0;I2=0;I3=0;EN=0; #50;

$finish;
end
endmodule

Please help me out.