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798 Views
Registered: ‎10-15-2018

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

Hi,

My Post implementation functional simulation is exiting with the below error -

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 331305100 ps  Iteration: 0  Process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/addr_c_i_p0_reg[1]_i_1/Always100_607
  File: /opt/Xilinx/Vivado/2018.2/data/verilog/src/unisims/LUT6.v
run: Time (s): cpu = 00:01:24 ; elapsed = 00:12:04 . Memory (MB): peak = 9891.965 ; gain = 0.000 ; free physical = 817 ; free virtual = 4512

Can anyone please help with what this seems to be coming from ?

Thanks and sincerely

Bhawandeep Singh

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5 Replies
Xilinx Employee
Xilinx Employee
785 Views
Registered: ‎07-16-2008

回复: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

Generally, fatal error is a tool issue.

You may want to trace it down to specific section of RTL based on the highlighted process, and see if there's any way to work around it.

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758 Views
Registered: ‎10-15-2018

回复: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

Hi graces,

Thanks for the informative reply, but is there any suggestion on what I can do ?

"Work-around" does not seem feasible since the error does not tell what the issue was.

Thanks and sincerely

Bhawandeep Singh

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Moderator
Moderator
745 Views
Registered: ‎05-31-2017

回复: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

Hi @bhawandeepsingh,

Please share a test case to reproduce the issue at our end and debug further.

668 Views
Registered: ‎10-15-2018

回复: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

For now, We have an LTE IP implemented on Virtex 6 using ISE, we are porting it to Zynq in ISE and then importing the project into Vivado (without Coregen IPs ugrade). Then I try to do post implementation simulation and this error comes for an LUT as mentioned - always at the exact same simulation time stamp.

What are some frequent/possible cases in which simulator exits with this ? Also, what does the below statement mean ?

run: Time (s): cpu = 00:01:24 ; elapsed = 00:12:04 . Memory (MB): peak = 9891.965 ; gain = 0.000 ; free physical = 817 ; free virtual = 4512

To add information - we are running simulation on individual machines (not on server) with 16GB RAM.

What more information do I need to provide ? Do you mean information related to our IP and testbench or something specific related to Vivado ?

 

 

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Observer cskuwahara
Observer
598 Views
Registered: ‎07-02-2018

回复: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

I'm working with Bhawandeep.  I ran the same design through Questa and encountered the following error at 331 us in the post-implementation simulation.

#############  Autofindloop Analysis  ###############
#############  Loop found at time 331305100 ps ###############
#   Active process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/\addr_c_i_p1_reg[8]_i_2 /<anonymous> @ sub-iteration 0
#     Source: downlink_top_tb_func_impl.v:1416163
#   Active process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/\addr_c_i_p1_reg[8]_i_14 /<anonymous> @ sub-iteration 0
#     Source: downlink_top_tb_func_impl.v:1416153
#   Active process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/\addr_c_i_p1_reg[8]_i_2 /<anonymous> @ sub-iteration 1
#     Source: downlink_top_tb_func_impl.v:1416163
#   Active process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/\addr_c_i_p1_reg[8]_i_14 /<anonymous> @ sub-iteration 1
#     Source: downlink_top_tb_func_impl.v:1416153
#   Active process: /downlink_top_tb/downlink_top_wraprmodule/downlink_topmodule/mymoChannelEstimate_module/mymoChannelEstimatemodulen0m0/\addr_c_i_p1_reg[8]_i_2 /<anonymous> @ sub-iteration 2
#     Source: downlink_top_tb_func_impl.v:1416163
################# END OF LOOP #################
# ** Error (suppressible): (vsim-3601) Iteration limit 10000000 reached at time 331305100 ps.

At the line numbers in the netlist, there is instances of a LUT5 and LUT6 from the unisim library.  How can there be a loop at a LUT?  Does this message mean that we have a combinational loop in our design?

Thanks,

Craig Kuwahara

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