02-11-2019 11:59 PM
Ref to the attachment,
Q_reg_1 is the Q output of FDCE,
Q_i_1_n_0 is the D input,
CPU_CCLK is the clock.
Functional simulation works correctly.
No timing violation is reported related to the above FDCE.
During my post implementation simulation, FDCE fails to capture the D input, why?
And the actual result is not right, either.
The tool is vivado/2017.4
Thanks in advance,
02-19-2019 01:57 AM
Does your design meets timing? What is the expected input at that particular time interval and can you please check the value of the signal that is driving this flop input. Does the post implemented and synthesized functional simulation works fine?
02-20-2019 01:12 AM
The design meets timing, and the funtional simulaiton works fine. I didn't check the synthesised simulation.
Afterwards, I found that it actually work well in FPGA. I failed to observe it is due to low sample frequency.
But It is still weired that the post implementation simulation fails, the value of the signal that is driving the flop input is high and last for one cycle, the output keeps low all the time in the post implementation simulation.
02-28-2019 10:23 PM
Hi @zjywindwalk ,
Are you facing this issue in post implementation functional simulation or timing simulaiton? Can you please share a test case to check this issue at my end.