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Adventurer
Adventurer
9,403 Views
Registered: ‎09-07-2015

FFT Core Vivado Simulation

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Hi,

 

I get an error when add fft test bench(vivado generate) vhd file into my sim sources. And fft ip core marked as red question.

 

 

 

fft_core.jpg

 

fft_sim.jpg

 

 

 

 

 

How can i fix this problem? Or how can i add auto generate tb into my project.

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Adventurer
Adventurer
17,637 Views
Registered: ‎09-07-2015

I suppose ; the problem is about the wrapper.

Auto generated test bench file instantiate design_1_xfft_0_0 not wrapper.

Both wrapper and tb instantiate design_1_xfft_0_0. Become circular reference problem.Beacuse of top level is wrapper not tb.

 

If you make hdl project not block design. You can test tb and fft core. it works!!

 

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3 Replies
Xilinx Employee
Xilinx Employee
9,398 Views
Registered: ‎08-01-2008
can you please share design file . It seems project not finding file . You may regenerate the IP
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
9,393 Views
Registered: ‎09-07-2015

Hi,

 

I did that;

 

1) Add FFT Core to BD

2) Generate Wrapper

-> It automatically add all desgin sources(wrapper,bd,..)  to sim sources

3) Generate Block Design

-> It generates a sim test bench inside working folder

4) Add test bench to sim sources

 

fftcore.jpg

 

 

 

 

 

 

 

 

 

 

 

 

 

fftroot.jpg

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Highlighted
Adventurer
Adventurer
17,638 Views
Registered: ‎09-07-2015

I suppose ; the problem is about the wrapper.

Auto generated test bench file instantiate design_1_xfft_0_0 not wrapper.

Both wrapper and tb instantiate design_1_xfft_0_0. Become circular reference problem.Beacuse of top level is wrapper not tb.

 

If you make hdl project not block design. You can test tb and fft core. it works!!

 

View solution in original post