08-25-2020 11:05 AM
I have a simple FIFO re-used in a few places in out design.
16-bits wide, 256 deep, asynchronous, implemented in Distributed Ram.
Write Clock: 120 MHz
Read Clock: 320 MHz
Implementation timing summary says all timings are met.
I have a case where the SLOW corner timesim shows the empty signal drop for one readclk cycle when it should not.
There is a write active at the same time, but empty should take synchronization cycles to propagate.
Due to the one-cycle error on empty, our logic reads the next entry - but since the FIFO had not actually propagated the write thru yet, the read just gets old data.
I attached a screenshot of the condition.
Wondering if I should consider it a real failure ... What could cause this? From experience, the simulator is pretty accurate.
I can probably accommodate the additional latency, and 1 cycle block on empty, but this is a very nasty bug.
10-15-2020 03:37 AM
Hi @tz_rrt ,
Do you see expected behavior in behavioral simulation for FIFO?
Can you please share a test case to check this issue?
11-17-2020 01:34 PM