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alfamanager
Observer
Observer
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Registered: ‎01-19-2021

FIFO Generator AXI Stream Interface Simulation Problem

Hello guys!

I want to see simple simulation of FIFO Generator 13.2 with AXI-Stream.

When I use this IP-Core, my simulation is not resulting properly.

How could I simulate this IP-Core without connect anywhere.

You can see the codes also.

xilinkforum.png

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dpaul24
Scholar
Scholar
367 Views
Registered: ‎08-07-2014

@alfamanager ,

You see the tvalid and tready signals? They should not be Xs. It should be driven.

Also I see that in your testbench, the axis signals are first driven and then you are driving resetn to high. Design should be brough out of reset first and then the AXIS signals should be driven.

btw - I told you in a similar post yesterday to look at the example_design testbench in the FIFO Generator AXI Stream Xilinx docu. Did you study it?

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alfamanager
Observer
Observer
350 Views
Registered: ‎01-19-2021

 I saw the example design but I need vhdl testbench I couldn't understand that. I need simple one IP-Core sim.

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