01-20-2021 11:19 AM - edited 01-20-2021 11:19 AM
01-20-2021 11:33 AM - edited 01-20-2021 11:37 AM
You see the tvalid and tready signals? They should not be Xs. It should be driven.
Also I see that in your testbench, the axis signals are first driven and then you are driving resetn to high. Design should be brough out of reset first and then the AXIS signals should be driven.
btw - I told you in a similar post yesterday to look at the example_design testbench in the FIFO Generator AXI Stream Xilinx docu. Did you study it?
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