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jmadill
Visitor
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Registered: ‎04-22-2015

FIFO Generator Compile Error

I am trying to run a simulation through vivado 2014.4 in active hdl 10.2. 

 

In my block diagram I have a AXI4-Stream Data Fifo. When I try to simulate my project I get an error when trying to compile the "fifo_generator_v12_0_vh_rfs.vhd"

 

The following are the errors that are showing up in the compile.log file

# Error: COMP96_0078: ../../../../../test_project.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vh_rfs.vhd : (33751, 19): Error in encrypted code.
# Error: COMP96_0134: ../../../../../test_project.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vh_rfs.vhd : (33751, 19): Error in encrypted code.
# Error: COMP96_0078: ../../../../../test_project.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vh_rfs.vhd : (33751, 17): Error in encrypted code.
# Error: COMP96_0134: ../../../../../test_project.srcs/sources_1/ip/fifo_generator_0/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vh_rfs.vhd : (33751, 17): Error in encrypted code.

Anyone have any suggestion to fix this problem?

 

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graces
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Registered: ‎07-16-2008

Please have a look at the following AR.

http://www.xilinx.com/support/answers/64085.html

 

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jmadill
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Registered: ‎04-22-2015

I have done everything in that document before I posted this thread, also I downloaded vivado 2015.1 to see if that make a difference and it does not because I still get that error.

 

One thing to note is if I open up the project manually in active-hdl and run the same commands out of the simulation_compile.do file the simulation works. 

 

Also I can have a active-hdl instance runnin before telling vivado to run simulation. Once I hit the run simulation button vivado opens up another active-hdl instance it will compile everything and still error out on the fifo generator file, then close active-hdl window and then open up another active-hdl and perform the simulation.

 

I am just trying to figure why active-hdl keeps erroring out on the fifo_generator_v12_vh_rfs.vhd file

 

 

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markcurry
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Registered: ‎09-16-2009

 

We've hit these stupid problems too with the (very frustrating) Xilinx fifo_generator core.  (And other cores as well)

It's going to get worse as Xilinx moves to the "encrypt everything" mentality.  Sigh.

 

Anyway it's likely related to Xilinx' overuse of (too darned many) VHDL libraries creating compile order problems.  You'll likely need to change it around to resolve.  Without actually being able to actually see the error (because of the stupid encryption) you're left with a shotgun approach of just changing things around randomly until it works.

 

I can't offer much else other than keep trying to hack away.  We keep getting the same errors here on our end - they almost seem to occur randomly (i.e. without tool upgrades).  We hack away, resolve the problem, and forget it until next time.

 

Good luck.

 

--Mark

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graces
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Registered: ‎07-16-2008


@jmadill wrote:

I have done everything in that document before I posted this thread, also I downloaded vivado 2015.1 to see if that make a difference and it does not because I still get that error.

 

One thing to note is if I open up the project manually in active-hdl and run the same commands out of the simulation_compile.do file the simulation works. 

 

Also I can have a active-hdl instance runnin before telling vivado to run simulation. Once I hit the run simulation button vivado opens up another active-hdl instance it will compile everything and still error out on the fifo generator file, then close active-hdl window and then open up another active-hdl and perform the simulation.

 

I am just trying to figure why active-hdl keeps erroring out on the fifo_generator_v12_vh_rfs.vhd file

 

 


If the standalone simulation flow works fine, the compilation commands should be good. 

When you run simulation in Active-HDL alone, did you use the exact commands from simulation_compile.do including the file path names?

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jmadill
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Registered: ‎04-22-2015


@markcurry wrote:

 

We've hit these stupid problems too with the (very frustrating) Xilinx fifo_generator core.  (And other cores as well)

It's going to get worse as Xilinx moves to the "encrypt everything" mentality.  Sigh.

 

Anyway it's likely related to Xilinx' overuse of (too darned many) VHDL libraries creating compile order problems.  You'll likely need to change it around to resolve.  Without actually being able to actually see the error (because of the stupid encryption) you're left with a shotgun approach of just changing things around randomly until it works.

 

I can't offer much else other than keep trying to hack away.  We keep getting the same errors here on our end - they almost seem to occur randomly (i.e. without tool upgrades).  We hack away, resolve the problem, and forget it until next time.

 

Good luck.

 

--Mark


I tried to rearrange the files manually, i actually compiled everything but the fifo_generator_v12_0_vh_rfs file first and then compiled the fifo generator file and it still errored out. I am not sure what other file I am missing. The only two fifo_generator files that are in the compile script are:

        - simulation/fifo_generator_vhdl_beh.vhd

        - hdl/fifo_generator_v12_0_vh_rfs.vhd

 


@graces wrote:

 

If the standalone simulation flow works fine, the compilation commands should be good. 

When you run simulation in Active-HDL alone, did you use the exact commands from simulation_compile.do including the file path names?


Yes it works, but I still think that this file needs to be fixed or someone tell us which file is missing so I can compile it first.

 

For now I will just work around it by just creating the compile and simulation scripts and manually running it in active-hdl

 

-James

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eml
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Registered: ‎03-31-2017

What a pain. The simplest answer I found is to create an example design in the GUI, and get the compilation order from that.

 

Open the GUI, Manage IP, right-click your FIFO core, Open IP example design. In the new example design window, go to Flow, run simulation. Running with the Vivado simulator is Ok. You can find the compilation order in the logs, but the flow has now created

 

[core]_example.ip_user_files/sim_scripts/[core]

 

This contains scripts for Incisive, ModelSim, and VCS. No Aldec, but the Modelsim script is attached. Ignore xil_defaultlib - this will just be your work library. So, in short, create fifo_generator_v13_0_1, and then compile simulation/fifo_generator_vhdl_beh.vhd and hdl/fifo_generator_v13_0_rfs.vhd into it, in that order, as you've already found out, and then compile the top-level behavioural file into work along with your test.

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