FIFO_SYNC_MACRO simulation model squelching output when DO_REG=1

[zhouflyer]

  I'm doing fuctional simualtion with the FIFO functional simulation model from Xlinx(FIFO_SYNC_MACRO.v). When DO_REG is set to 1. The outputdata of the FIFO will be squelched. By checking the codes of the file,  I find there's an issue related to this case.

   Original code of Line 184 is " assign RSTREG_PATTERN = DO_REG ? 1'b1 : 1'b0;  "

   It should be        "assign RSTREG_PATTERN = DO_REG ? 1'b0 : 1'b1;"

[pthakare]

HI @zhouflyer 

Can you please share the Simulations screenshot depecting this behaviour ?

Are you getting output dont care or any fixed value?

[zhouflyer]

 I define the data signal as bit[xxx:0] when instatiate the FIFO_SYNC_MACRO , so the squelched data is always 0. Actually the internal signal value is always xxx.  I think the issue is a clerical but fatal err.

[fshenmi]

Is this problem resolved? My version is 2019.1

I ran into the same issue. Looks like this bug gets propagated into implementation as well. 

I try to edit the verilog and VHDL file and clean and rerun the simulation. But this didn't help.