cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
9,223 Views
Registered: ‎02-04-2013

FIFO simulation

Jump to solution

I am trying to simulate FIFO i generated with wizard in Vivado 2015.3. The simulation shows some result i was not expecting.

 

I set the wr_en <= '1' and din <= x"12" to simulate the behaveour (please see image below). What seems strange to me is that:

- it lasted 5 clock cycles for something to happen

- after that "full" signal changed its state to "X" - i was expecting '0' and '1'

- when i try to rd_en <= '1', the "empty" signal goes from 1 to "X".

 

Is this normal behaviour of fifo (please see image)?

 

Regrds

Klemen

 

fifosim.png

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
17,433 Views
Registered: ‎07-18-2011

Re: FIFO simulation

Jump to solution

I recommend that you assert the FIFO's rst signal at the beginning of your simulation.

 

View solution in original post

0 Kudos
5 Replies
Highlighted
Explorer
Explorer
17,434 Views
Registered: ‎07-18-2011

Re: FIFO simulation

Jump to solution

I recommend that you assert the FIFO's rst signal at the beginning of your simulation.

 

View solution in original post

0 Kudos
Highlighted
Moderator
Moderator
9,187 Views
Registered: ‎06-24-2015

Re: FIFO simulation

Jump to solution

Hi @fogl,

 

Try to make reset '1' for few ns at the start of simulation, then make it '0' again and then try.

 

Thanks,
Nupur

---------------------------------------------------------------------------------------------------------------------

Accept as solution if it resolved your query, give kudos if it led you to the solution.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
Highlighted
Participant
Participant
9,164 Views
Registered: ‎04-05-2014

Re: FIFO simulation

Jump to solution

You should also check the initial value of your rd_en signal.

From the waveform one can see that it is uninitialized until the first clock edge, so that is also what the fifo will see on the first rising edge.

 

A reset as @nupurs suggested should also fix the problem.

0 Kudos
Highlighted
Explorer
Explorer
9,144 Views
Registered: ‎02-04-2013

Re: FIFO simulation

Jump to solution

Thank you, reset solved the problem.

 

Is reset at the start also usual design practice for the implementation in the fpga?

0 Kudos
Highlighted
Contributor
Contributor
8,584 Views
Registered: ‎12-07-2015

Re: FIFO simulation

Jump to solution

Usually it is a good practice to start any RTL design with a reset because it is the only way to initiailize the registers.

For this particular case, the FIFO requires 5 cycles of reset on following 5 cycles of no active use. I don't know exactly why this is the case, but it probably has to do with initializing the registers that control the FIFO block.