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3,839 Views
Registered: ‎12-07-2016

FIR Simulation very slow with Vivado 2017.1

Hello,

 

I try to run my simulation which contains some FIR Compiler Cores.

It's very frustrating because the eleborate step need around >20 mins.

 

WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1982]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1983]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1984]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1974]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1975]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1976]
Compiling architecture synth of entity fir_compiler_v7_2_8.calc [\calc(c_xdevicefamily="zynq",c_p...]
Compiling architecture synth of entity fir_compiler_v7_2_8.addsub_mult_add [\addsub_mult_add(c_xdevicefamily...]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1982]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1983]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1984]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1974]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1975]
WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [<PATH>/bd/duc_debug/ipshared/3d01/hdl/xbip_utils_v3_0_vh_rfs.vhd:1976]

All FIR together have maybe ~30 DSPs. Without the FIR cores the simulations takes just a few seconds.

I run Vivado 2017.1 on a Windows 7 64 Bit machine.

 

Have someone a idea how I can speed up the simulation step?

 

Thank you!

4 Replies
Contributor
Contributor
3,712 Views
Registered: ‎07-04-2016

Re: FIR Simulation very slow with Vivado 2017.1

The only solution that comes in my mind is to Right click on each DSP and "set as Out of Context for synthesis", if possible. 

This generates once and uses them in new synthesis runs (if nothing has changed). 

But as I remember it was not able to perform this operation on IP if it used generics, hope this is still not the case.

 

 

if this is the case, what if you create new IP with those DSPs and some necessary logic (and with no generics parameters) and set that as out of context. but before doing that to all 30 dsps, try on 1-2 dsp see if "out-of-context" works on it.

 

 

of if you are only changing only memory(BRAM, DDR) and then resynthesising, try changing only those memory elements, that can be done without regenerating bitstream https://www.xilinx.com/support/answers/63041.html

 

 

I have only those ideas.

0 Kudos
Explorer
Explorer
3,624 Views
Registered: ‎09-13-2011

Re: FIR Simulation very slow with Vivado 2017.1

See this too.

With a FIR model in the simulation the compile time (elaborate step) gets extremely long. Once running the simulation is pretty slow too but not that much of a problem. With a FIR model in VHDL the compile time and simulation time is so much faster.

 

Scholar mistercoffee
Scholar
3,535 Views
Registered: ‎04-04-2014

Re: FIR Simulation very slow with Vivado 2017.1

I have this problem too. It's ridiculous, like you say, >20 mins to elaborate. 

 

Has this been fixed in 2017.2? Or is there a fix?

Visitor bbtaylr
Visitor
3,069 Views
Registered: ‎04-19-2014

Re: FIR Simulation very slow with Vivado 2017.1

This is still a problem with 2017.2