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Visitor baldwin
Visitor
736 Views
Registered: ‎01-21-2018

FSM States show up as "U" in waveform simulation

ENTITY Lab2s_FSM IS
     Port (Input : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
           Clk : in  STD_LOGIC;
           Permit : out  STD_LOGIC;
           ReturnChange : out  STD_LOGIC);
END Lab2s_FSM;

ARCHITECTURE Structural OF Lab2s_FSM IS
    SUBTYPE Statetype IS std_logic_vector(3 DOWNTO 0);
    CONSTANT S_Off : Statetype := "0000";
    SIGNAL cs, nextstate: Statetype;
begin    

    CombLogic: Process (cs, Input)
    begin
        nextstate(3) <= ((not cs(3)) and (not cs(1)) and Input(2) and (not Input(1)) and (not Input(0))) or 
        ((not cs(3)) and (not cs(0)) and Input(2) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(1)) and cs(0) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and cs(2) and cs(1) and (not cs(0)) and (not Input(2)) and (not Input(1)) and Input(0)) or
        ((not cs(3)) and cs(2) and cs(1) and (not cs(0)) and (not Input(2)) and Input(1) and (not Input(0))) after 5.6 ns;
        
        nextstate(2) <= ((not cs(3)) and (not cs(2)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(1)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(0)) and Input(2) and Input(1) and Input(0)) or 
        ((not cs(3)) and (not cs(2)) and cs(0) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and cs(0) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and cs(1) and (not Input(2)) and (not Input(1)) and Input(0)) or
        ((not cs(3)) and (not cs(2)) and cs(1) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(1)) and (not Input(2)) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(0)) and (not Input(2)) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and cs(1) and cs(0) and Input(2) and (not Input(1)) and (not Input(0))) after 5.6 ns;
        
        nextstate(1) <= ((not cs(3)) and (not cs(2)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(1)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(0)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(1)) and (not cs(0)) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and cs(1) and (not cs(0)) and (not Input(2)) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and cs(1) and cs(0) and (not Input(2)) and (not Input(1))) or
        ((not cs(3)) and (not cs(2)) and cs(1) and cs(0) and (not Input(2)) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and cs(1) and cs(0) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(1)) and (not Input(2)) and (not Input (1)) and Input(0)) after 5.6 ns;
        
        nextstate(0) <= ((not cs(3)) and (not cs(2)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(1)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(0)) and Input(2) and Input(1) and Input(0)) or
        ((not cs(3)) and (not cs(1)) and cs(0) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and (not cs(2)) and (not cs(0)) and (not Input(2)) and (not Input(1)) and Input(0)) or
        ((not cs(3)) and (not cs(2)) and cs(0) and (not Input(2)) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(1) and (not cs(0)) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and cs(1) and (not cs(0)) and Input(2) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(0)) and (not Input(2)) and Input(1) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(1)) and Input(2) and (not Input(1)) and (not Input(0))) or
        ((not cs(3)) and cs(2) and (not cs(1)) and cs(0) and (not Input(2)) and (not Input(1))) after 5.6 ns;
        
        Permit <= (nextstate(3) and (not nextstate(2)) and (not nextstate(1)) and (not nextstate(0)));
        ReturnChange <= ((not nextstate(3)) and nextstate(2) and nextstate(1) and nextstate(0)) or
         (nextstate(3) and (not nextstate(2)) and (not nextstate(1)) and (not nextstate(0))); 
      end process CombLogic; 
          
StateRegister: Process (Clk)
    begin
        if(Clk = '1' and Clk'EVENT) then
            cs <= nextstate after 5.6 ns;
        end if;
    end Process StateRegister;       


END Structural;

This is my code. I know U means uninitialized, but I'm not sure how. I tried setting permit, returnchange, nextstate, and cs all to 0 or 0000 like so: 

    Permit <= '0';
    ReturnChange <= '0';
    nextstate <= "0000";
    cs <= "0000";

but then the waveform just returns a couple X's, although it is heading in the sort of right direction I think.

a.PNG

I'm sure no one is going to be bother to check through the boolean equations, but I'm building a basic vending machine that accepts cash and returns change or dispenses a permit based on if the cash is $20 or more. '

 

Thanks!

Tags (1)
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2 Replies
Scholar jmcclusk
Scholar
707 Views
Registered: ‎02-24-2014

Re: FSM States show up as "U" in waveform simulation

give an initial value for your signals:

 

SIGNAL cs, nextstate: Statetype := S_off;
Don't forget to close a thread when possible by accepting a post as a solution.
Visitor baldwin
Visitor
695 Views
Registered: ‎01-21-2018

Re: FSM States show up as "U" in waveform simulation

Thank you, this solved it!

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