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Explorer
Explorer
1,079 Views
Registered: ‎11-21-2013

FWFT FIFO empty signal - low after reset signal when using post-synthesis functional or timing simulation

Hey, Dear All,

 

I am using a FWFT fifo in my testbench, and when using behavior simulation, the empty signal of the FIFO is set to high after the reset;  however when using post-synthesis simulation, no matter is functional or timing, the empty signal of the FIFO is set to low after the reset.

 

How should I fix this problem?

 

Thank you!

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Moderator
Moderator
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Registered: ‎04-24-2013

HI @xubintan,

 

Can you supply more information, what version of the tools are you using?

Do you have a small test project that shows the issue?

Best Regard
Aidan

 

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Explorer
Explorer
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Registered: ‎11-21-2013

hi, @amaccre,

 

Sorry I think I misunderstood the problem, when I launch post-synthesis simulation, the FWFT FIFO I used in the testbench does not even show up.

 

As can be seen, in Sim_src, only PICOS_HW_UUT are design files, and this is the top of the custom IP.

Other files are for testing, the READYTASK_UUT is a FWFT FIFO that is initialized inside the tb_picos_hw file.

 

When launching pre-synthesis behavior simulation, you can see in the Pre-synthesis.png, all the files shown on top are inside.

 

When launching post-synthesis simulation in Post-synthesis.png, the two FIFOs used are missing. That is probably why the FIFO empty signal is wrong.

 

Do you know where I can find answers on how to correctly do the Post-synthesis?

Thank you!

 

 

Sim_src.png
Pre-synthesis.png
Post-synthesis.png
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Moderator
Moderator
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Registered: ‎04-24-2013

Hi  @xubintan,

 

Looking at your screen shots in the Behavioural simulation you have set tb_picos_hw as the top, but in the Post Synthesise simulation you have set PICOS_HW_UUT as top. You can see this by which item is highlighted in Bold.

 

I created the FIFO example design and ran the simulation, the structure is the same between them all.

 

Beh_Sim.JPG

 

Post_Synth_Functional.JPG

 

Post_Synth_TIming.JPG

 

The only difference in the two post synthesis simulations are that the Timing simulation is using Verilog modules as only Verilog is supported for timing simulations.

 

Best Regards
Aidan

 

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Explorer
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Registered: ‎11-21-2013

Hi, @amaccre

 

For here "

Looking at your screen shots in the Behavioural simulation you have set tb_picos_hw as the top, but in the Post Synthesise simulation you have set PICOS_HW_UUT as top. You can see this by which item is highlighted in Bold.

"

Actually it is no, in the post synthesis simulation it is just my mouse is clicked on "PICOS_HW_UUT", and that is why it is bold.

 

So in the attachments you will find the screenshot that I rested my mouse over "tb_picos_hw", and now it is bold.

 

It is just in my custom IP case, I don't know why the other two FIFO IP that are initiated inside tb_picos_hw are missing when I launch post-synthesis simulation.

 

 

post-synthesis-2.png
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