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Visitor raul2009
Visitor
10,858 Views
Registered: ‎03-04-2009

Failed to link the design Process will terminate

Hi everyone, I am trying to link VHDL and modelsim, but the following error appear

 

FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 21:25:47 sonals Exp $ - Failed to link the design   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

 

I have reinstall and install the VHDL and modelsim, but the error keep appear, any help please ? thank you very much

 

 

 

Running Fuse ...
fuse -intstyle ise -incremental -o ANC_tb_isim_beh.exe -prj ANC_tb_beh.prj -top ANC_tb
Determining compilation order of HDL files
Analyzing VHDL file counter.vhd
Restoring VHDL parse-tree ieee.std_logic_1164 from c:/moldelsim/ise/vhdl/hdp/nt/ieee/std_logic_1164.vdb
Restoring VHDL parse-tree std.standard from c:/moldelsim/ise/vhdl/hdp/nt/std/standard.vdb
Restoring VHDL parse-tree ieee.std_logic_arith from c:/moldelsim/ise/vhdl/hdp/nt/ieee/std_logic_arith.vdb
Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/moldelsim/ise/vhdl/hdp/nt/ieee/std_logic_unsigned.vdb
Analyzing VHDL file ANC_tb.vhd
Restoring VHDL parse-tree ieee.numeric_std from c:/moldelsim/ise/vhdl/hdp/nt/ieee/numeric_std.vdb
Saving VHDL parse-tree work.counter into c:/documents and settings/nelson delemos/project/isim/work/counter.vdb
Saving VHDL parse-tree work.anc_tb into c:/documents and settings/nelson delemos/project/isim/work/anc_tb.vdb
Starting static elaboration
WARNING:HDLCompiler:746 - "N:/K.31/rtf/vhdl/src/ieee/numeric_std.vhd" Line 867. Range is empty (null range)
WARNING:HDLCompiler:746 - "N:/K.31/rtf/vhdl/src/ieee/numeric_std.vhd" Line 868. Range is empty (null range)
Completed static elaboration
Fuse Memory Usage: 55864 Kb
Fuse CPU Usage: 1186 ms
Using precompiled package standard from library std
Using precompiled package std_logic_1164 from library ieee
Using precompiled package std_logic_arith from library ieee
Using precompiled package std_logic_unsigned from library ieee
Using precompiled package numeric_std from library ieee
Compiling architecture behavioral of entity counter [counter_default]
Compiling architecture behavior of entity anc_tb
FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 21:25:47
   sonals Exp $ - Failed to link the design   Process will terminate. For
   technical support on this issue, please open a WebCase with this project
   attached at http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 21:25:47 sonals Exp $ - Failed to link the design   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

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2 Replies
Xilinx Employee
Xilinx Employee
10,830 Views
Registered: ‎08-15-2007

Re: Failed to link the design Process will terminate

Hello,

 

Please review the solutions shown in Xilinx Answer 31866

 

By the way, you appear to be launching a simulation using ISE Simulator, not ModelSim.  Re-installing ModelSim would not address this issue.  If you intend to lauch a simulation using ModelSim, make sure you have selected ModelSim as your HDL simulator of choice.  This is done by right-clicking on the device part name and clicking on "Properties ..."

 

Hope this helps.

Eddie
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Visitor vkantamn
Visitor
7,082 Views
Registered: ‎10-10-2012

Re: Failed to link the design Process will terminate

hallo edv,

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.129 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 587 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

I dont really understand why I get this. The code is itself synthesizable. :(

Please help me if you have got any suggestion.
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