I found an identical post marked SOLVED using v2016.1 tools. I have encountered the same problem using 2017.1:
DRC Error : DRPEN is enabled before DRPRDY returns on top_sim.inst_top....
** Note: $finish : F:/Xilinx/Vivado/2017.1/data/verilog/src/unisims/GTXE2_CHANNEL.v(2593)
When compiling the core the only DRP options are 'Use Common DRP' which is unchecked, and 'Use DRP' on the 'Encoding and Clocking' tab which is checked and greyed out so it cannot be changed.
In the design all DRPEN pins are permanently tied low. I attempted tying DRPWE pins high and low as an experiment with the same result.
Device is Virtex XC7VX485TFFG on VC707 board. GTX core compiled using '7 Series FPGAs Transceivers Wizard' 3.6 (Rev 6) and simulating on Mentor Questa Sim-64 10.5c.