Fixed point in VHDL program using ModelSim

[coder123]

I should work with inputs like : -0.3016957 in my VHDL program and when I do my researchs I found that I should work with fixed point and I call this library library ieee_proposed; in my code but the problem is it gives me an error that ieee_proposed is not found or known.

So the question is how can I import this library in my project ?

[drjohnsmith]

Multiple questions here,

Are you using modelsim ? which version ?
what software tool are you using to design the part ?

A number such as -0.3016957 , can not be expressed as a base 2 number,

The position of the "point" in any number is in the eye of the beholder. So for-intance
if you have a number made out of 8 bits ,
then that could be no sign , one bit as the integer part, and the other 7 as the fractional part, That would have range 0 to almost 2.

Or if you have a number made out of 8 bits ,
then that could be one sign , two bit as the integer part, and the other 5 as the fractional part, That would have range -3 to almost +3

So first up Id suggest you experiment with adding number in VHDL

http://userweb.eng.gla.ac.uk/scott.roy/DCD3/05_Arithmetic.pdf

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf


If you want to use fixed point,

The older version of VHDL, before 2008, did not have fixed point numbers, So various none IEEE packages were invented, including the one you have seen,
.
In VHDL 2008 and later, fixed_point is included as standard,

BUT, Xilinx does not support VHDL very well, we think all their work is done in Verilog or C

https://forums.xilinx.com/t5/Synthesis/Fixed-point/td-p/940307

[coder123]

I am using ModelSim-Altera 10.1d (Quartus II 13) and my numbers are coded in 11 bits.

Is the fixed point exist just in vhdl 2008 ?? or I can work with it in my version of modelsim ?

I should load a vector of this kind of numbers and then do some operations with them like calculate the average ?

So should I use the fixed point or not ?

if you any advise you are welcome

[drjohnsmith]

I was wondering,

As this is a Xilinx forum , I suggest you ask this on the intel forum that supports the altera / Quartus devices.

https://forums.intel.com/s/?language=en_US

[richardhead]

ieee_proposed was a library that was setup to allow 2008 feature libraries written in VHDL 1993 language to allow people to use them while there was no compatible tools.

Its now 2020 (12 years later) and VHDL 2008 has very good support. Forget about ieee_proposed and just used ieee library:

library ieee;
use ieee.fixed_pkg.all;

You will need to turn on 2008 compatability to do this. You may need to use a newer version of modelsim

[drjohnsmith]

You will need to check with Intel as to does your version of modelsim support 2008 Despite Richards optimism, its not that well supported, but to be fair, modelsim is better than some simulators at it, if you get the right version,

[richardhead]

Vhdl 2008 is well supported by all tools.  xilinx is just way behind everyone else. The main simulators are usually the first to get new support. Modelsim got 2008 support in 10.0. Activehdl has some vhdl2019 support in the latest release. All synth tools now have decent 2008 support.

[coder123]

Thank you so much for your time 

So what I understand from your answers is the IEEE library is enough for my version of modelSim and I should use UNSIGNED for float numbers 

[richardhead]

Floating point are different from fixed point.

Floating point is a N bit number with a mantissa and exponent. https://en.wikipedia.org/wiki/Floating-point_arithmetic

The implementation of floating point in FPGA is expensive and high latency.

Fixed point is just an integer offset by 2^N. This can be done cheaply in an FPGA using integer arithmatic.

for example, 2.75 can be represented as a 4 bit unsigned integer, which is offset by 2^N.

2.75 = 1011 (11 in decimal) / 2^2.

You can do this using unsigned, but you need to manually ensure that all integer/fraction separatations are aligned manually by manually zero/sign bit padding to maintain alignment.

The fixed_pkg provided in VHDL 2008 (and from the ieee_proposed) provides more useful types ufixed and sfixed, where the integer/fraction separation is built into the type, and bit alignment is all handled for you:

signal s4_4 : sfixed(3 downto -4);
signal s8_1 : sfixed(7 downto -1);
signal s9_4 : sfixed(11 downto -4);

s9_4 <= s4_4 + s8_1;

Quartus prime pro has full 2008 support

As does Vivado 2019

[coder123]

input1  : in ufixed( 11 DOWNTO 0 );

 In my code there is an input it's type ufixed and I want to simulate the code via modelsim

I tested this but it does not working 

How can I modify it to test my code ?? 

[richardhead]

Dont use Forces - write a testbench.

[coder123]

Thank you very much for spending your time to replying. 

Do you have some resources to recommend for me in order to write a test bench in modelsim ?

I'm searching since yesterday but still found nothing useful.

[richardhead]

There are many resources around the web

https://lmgtfy.com/?q=how+to+write+a+testbench+in+vhdl

[drjohnsmith]

@coder123

do you not feel a little guilty
your using Altera tools and chips supported by Intel,
and your using the altera Modelsim, supported by Mentor,

This is a Xilinx forum .