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Visitor
Visitor
1,166 Views
Registered: ‎02-24-2018

Flip-Flop D abnormal behaviour

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Hi everyone,

 

I can't understand why some simple flip-flops are acting different from their normal behaviour. They don't respect the clock edges and the first of the two is even sampling different values from those is taking in input. Below there are the code of the FFs and the behavioural simulation.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity reg8bitf is
port ( D_r8 : in std_logic_vector(7 downto 0);
       CE_r8 : in std_logic;
       CLKD_r8: in std_logic;
       Q_r8 : out std_logic_vector(7 downto 0):=(others=>'0'));
end reg8bitf;

architecture Behavioral of reg8bitf is

begin
process(CLKD_r8)
begin
if (rising_edge(CLKD_r8) ) then
if (CE_r8='1') then
Q_r8 <= D_r8;
end if;
end if;

end process;

end Behavioral;
ff.png
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Xilinx Employee
Xilinx Employee
1,521 Views
Registered: ‎05-06-2008

Hello CV330,

 

I recommend opening a new thread on the timing closure type questions.  This will insure the correct experts will address your concerns.

 

Thanks,

Chris

View solution in original post

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4 Replies
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Scholar
Scholar
1,153 Views
Registered: ‎08-01-2012

You have only posted one peice of code. Where is the testbench that is generating the waveform? and why are there 2 sets of signals? you also didnt include CE on the waveform.

 

Please rephrase the question to something more coherent.

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Moderator
Moderator
1,149 Views
Registered: ‎03-16-2017

Hi @cv330

 

Based on your code i have tried behav. simulation. I did not find any issues. please have a look. 

 

b1.JPG

 

 

If you have a testbench on which you are facing issues, please provide.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor
Visitor
1,104 Views
Registered: ‎02-24-2018

Excuse me for the lack of data in my question. At the end i've got around the problem changing the structure of the circuit.

 

Now I have another question which however isn't related with this post, is about timing closure and high percentage of net delay with only 2 logic levels on the path. Can I show what i've got here or I have to open another thread?

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Xilinx Employee
Xilinx Employee
1,522 Views
Registered: ‎05-06-2008

Hello CV330,

 

I recommend opening a new thread on the timing closure type questions.  This will insure the correct experts will address your concerns.

 

Thanks,

Chris

View solution in original post

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