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Contributor
Contributor
3,206 Views
Registered: ‎01-27-2016

Formal port does not exist in entity

I designed a Gaussian interpolator using system generator. I changed some of the input and output bit widths, and now I am getting the following errors during elaboration in an effort to run a behavioral simulation.

ERROR: [VRFC 10-718] formal port <pk> does not exist in entity <gauss_interp_fxdpt>. Please compare the definition of block <gauss_interp_fxdpt> to its component declaration and its instantion to detect the mismatch. [C:/HDL/lpp_detect_rev1/lpp_detect_rev1.srcs/sources_1/ip/gauss_interp_fxdpt_0_1/sim/gauss_interp_fxdpt_0.vhd:74]
ERROR: [VRFC 10-718] formal port <pk_abv> does not exist in entity <gauss_interp_fxdpt>. Please compare the definition of block <gauss_interp_fxdpt> to its component declaration and its instantion to detect the mismatch. [C:/HDL/lpp_detect_rev1/lpp_detect_rev1.srcs/sources_1/ip/gauss_interp_fxdpt_0_1/sim/gauss_interp_fxdpt_0.vhd:75]
ERROR: [VRFC 10-718] formal port <pk_blw> does not exist in entity <gauss_interp_fxdpt>. Please compare the definition of block <gauss_interp_fxdpt> to its component declaration and its instantion to detect the mismatch. [C:/HDL/lpp_detect_rev1/lpp_detect_rev1.srcs/sources_1/ip/gauss_interp_fxdpt_0_1/sim/gauss_interp_fxdpt_0.vhd:76]
ERROR: [VRFC 10-718] formal port <frac_freq_op> does not exist in entity <gauss_interp_fxdpt>. Please compare the definition of block <gauss_interp_fxdpt> to its component declaration and its instantion to detect the mismatch. [C:/HDL/lpp_detect_rev1/lpp_detect_rev1.srcs/sources_1/ip/gauss_interp_fxdpt_0_1/sim/gauss_interp_fxdpt_0.vhd:78]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

I used the component and instantiation template for the core in my code. Below is the component definition in the code generated by System Generator:

 

COMPONENT gauss_interp_fxdpt IS
PORT (
pk : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
pk_abv : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
pk_blw : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
clk : IN STD_LOGIC;
frac_freq_op : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);

 

I read through the relevant postings on the forum, but I cannot find any differences between the component and instance definitions on the ports. Any ideas to what might be going on? One thing that I did notice is that a new directory is created for the System Generator design every time I modify the core and re-generate the output products. Should I delete the old directories? Thanks.

 

 

Bill

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2 Replies
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Xilinx Employee
Xilinx Employee
3,170 Views
Registered: ‎05-22-2018

Hi @centercitybill,

 

Please uncheck the incremental compilation option in the simulation settings, as shown in attached snapshot, it might help:

 

Capture112.JPG

 

Thanks,

Raj.

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3,150 Views
Registered: ‎01-22-2015

Hi Bill,

 

The errors you show look a little like errors I get for syntax problems when declaring/instantiating a VHDL component.  In the VHDL component declaration that you show, you have left out the required last line "end component ;", which would be a syntax error.

 

I also note that the last error you show says "...top level Verilog design unit(s) in library work failed".   Are you perhaps mixing VHDL and Verilog improperly?  Did you perhaps grab the VHDL instantiation template when you shoulda grabed the Verilog template?

 

Cheers,

Mark

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