08-30-2018 07:58 AM
I am having a problem understanding why the first read from an UltraRAM in a behavioural Simulation (using Modlesim DE and a VHDL design) is taking 4 clocks when it should be 1 ? Has anybody else seen / solve this issue please ?
Basically i have instantiated 3 UltraRAMs a s a row to provide x3 x72 = 216 bit words. My UltraRAM cores all have
IREG_PRE_A, IREG_PRE_B and OREG_A and OREG_B set as FALSE. So i was expecting to see the data D0 pop out of the read port the cycle after the port a address appears. (ENA_A = 1 and RDB_WR_A = 0).
That is not the case...as i increment address on read port a i see the data at output port a stay at the same value for address 0 for 4 clocks...then it changes correctly after each address increment and the port a output data changes on every clock cycle. But what is happening on the first memory read access ..why the 4 clock latency ?
thanks for your help,
Dr Barry H
09-03-2018 08:33 AM
Have you allowed for the GSR (global set reset) to clear?
This takes 100ns and is taken into account when you run a functional simulation and not the behavioural simulation.
The reason for this is that the functional simulation simulates real hardware, while the behavioral simulation simulates the HDL.
09-10-2018 01:07 AM
thanks for your reply. Yes i know about the GSR .... i have been caught out before with that one ! This time it was due to me not quite getting the right signals on my simulation ...i wasnt looking at the address at the lowest level of the core. When i did that things looked correct ! Thanks for your help anyway.
cheers, Dr Barryh