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Visitor dr_graham7
Visitor
470 Views
Registered: ‎06-19-2018

Functional Simulation wrong latency reading UltraRAM

Hello All,

I am having a problem understanding why the first read from an UltraRAM in a behavioural Simulation (using Modlesim DE and a VHDL design) is taking 4 clocks when it should be 1 ? Has anybody else seen / solve this issue please ?

 

Basically i have instantiated 3 UltraRAMs a s a row to provide x3 x72 = 216 bit words. My UltraRAM cores all have

IREG_PRE_A, IREG_PRE_B and OREG_A and OREG_B set as FALSE. So i was expecting to see the data D0 pop out of the read port the cycle after the port a address appears. (ENA_A = 1 and RDB_WR_A = 0).

 

That is not the case...as i increment address on read port a i see the data at output port a stay at the same value for  address 0 for 4 clocks...then it changes correctly after each address increment and the port a output data changes on every clock cycle. But what is happening on the first memory read access ..why the 4 clock latency ?

 

thanks for your help,

Dr Barry H

 

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2 Replies
Moderator
Moderator
418 Views
Registered: ‎04-24-2013

Re: Functional Simulation wrong latency reading UltraRAM

Hi @dr_graham7,

 

Have you allowed for the GSR (global set reset) to clear?

This takes 100ns and is taken into account when you run a functional simulation and not the behavioural simulation.

 

 

GSR.JPG

 

The reason for this is that the functional simulation simulates real hardware, while the behavioral simulation simulates the HDL.

 

Best Regards
Aidan

 

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Visitor dr_graham7
Visitor
365 Views
Registered: ‎06-19-2018

Re: Functional Simulation wrong latency reading UltraRAM

Hi Aidan,

thanks for your reply. Yes i know about the GSR .... i have been caught out before with that one ! This time it was due to me not quite getting the right signals on my simulation ...i wasnt looking at the address at the lowest level of the core. When i did that things looked correct ! Thanks for your help anyway.

 

cheers, Dr Barryh

 

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