07-21-2021 11:24 PM
I have written a function for the generation of 128-bit data in a Verilog module, when I generate bitstream then that function not running on the Hardware, but if I replace the function with a new module and instantiate it in the main Verilog code (working same as a function) then it's started working on Hardware. Can you please explain why this is happening?
07-21-2021 11:43 PM
Can you please explain why this is happening?
No absolutely not and I guess no one else also can't with so little info.
Write a testbench of your DUT and simulate the DUT. You will find the problem.
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