08-13-2012 02:43 AM
We are using xilinx ISE 12.3 tool (for spartan 6 Device )in our product.
We are using many internal cores (Block memories and FIFos and DCMs..etc).
We successfully verified our designs using questasim 6.4c (External simulator) using system verilog based test bench environment.
Now we wanted to test our application for Gatelevel verification using systemverilog test environment.
Please give us some advice and steps how to do gatelevel simulation using systemverilog environment.
Note: As design is almost 60%consumed in spartan 6 ( XC6slx25-3ftg256 ) and complex test cases so we are using systemverilog environment.
08-13-2012 06:34 AM
since you are using an FPGA you are not able to do anything on the "gate-level".
The only thing comparable to this would be a post-par-simulation.
For that you can create a netlist and delay file with ise that contains all the information according to the actual placement and connection of the FPGA internal elements with their timing informations.
(Process window: Implementation-> Place and route -> Generate post place and route netlist...)
This netlist needs to be instantiated in your SV-testbench and you need to start the simulation in a way that uses the SDF-file together with the HDL-netlist..
If your testbench is written correctly, so that the delayed signals cause no problems, everything should work just fine.
You will find many threads here describing problems and solutions that happen otherwise.
Have a nice simulation
08-13-2012 11:58 AM
The "gate-level" design is generated after PAR is done which gives you a netlist of the design as it will exist on the FPGA and a timing annotation file (SDF format the same as you get in the ASIC world).
At this point, the "gate-level" simulation is pretty similar to ASIC stuff. You point to the netlist for the design instead of the RTL and you do an sdf annotation to load the timing.
One warning is that name-mangling after par in fpgas is a lot more comprehensive ;-) than asics and any hierarchy is pretty much destroyed so here is to hoping that you are not peering into your design from your testbench.
08-13-2012 11:12 PM
08-14-2012 12:19 AM
what's causing that confusion?
ISE is not supporting System Verilog for now.
Still you can choose Questa as your Simulator tool in the ISE Project properties.
Even if you have no testbench (just for this example) you can do all the steps for a post_par_simulation in the same way you would do with ISIM.
After that you find some *.fdo file in your project directory. It should have something like "timesim" in the filename.
This is a Modelsim/Questasim do file. When you open it in an editor you find a line there with the vsim command.
There you can see all the parameters used for adding the SDF file etc. Then you can add these to your own *.do file that controlls your SV-verification run.
I assume that you know how to work with Questasim *.do files.
If not, you better get used to it. Use the automatically generated *.fdo file as a starting point.
Have a nice simulation
08-20-2012 12:29 PM
I would make sure the libraries are compiled and referenced correctly as pointed out in this document on page 163/173 .
Timing simulation uses the simprim libraries, so you must make sure and reference those. The flow is identical for Questa as for Modelsim.
Hope this helps ...