02-17-2010 08:20 AM
I'm running ModelSim PE 6.6, and using ISE 10.1 (it's old, but works). I'm doing a gate level simulation but the DCM simulation is not right. There is a 2.3 ns delay for the clock input to the DCM, which results in the output clock of the DCM and my input clock not being locked. The clock that is being fed is 100 Mhz, so 2.3 ns throws everything out of wack. Has anyone seen this problem and have a work around ? I'm tempted to edit the .sdf file..
02-18-2010 01:32 PM - edited 02-18-2010 01:33 PM
Rather than editing the SDF file, I would recommend upgrading to 11.4. There is not enough detail to know if this is a known issue in 10.1, although I remember when in the first release of 10.1 we had a bug in the DCM lock that we fixed in one of the service packs.
09-26-2010 04:03 AM
The Possible reasons for DCM not locking might be due to one of the below
Also http://www.xilinx.com/support/troubleshoot/clocking_debug.htm link helps for debugging