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Observer ahmadian
Observer
8,883 Views
Registered: ‎05-03-2015

Generics in testbench

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Hello, 

 

I'm currently simulating a UUT (I'll call it "A" in this message) which is configurable by generics. As I have to instantiate several of this component in the target hardware, I have to instantiate them with different generics. Therefore, I'm instantiating this component in an intermediate entity (which I call it "B.vhd") and is used only for the simulation. Finally I instantiate this entity (B) in the testbench (let's call it "C_tb.vhd") which doesn't have any generics. 

To summerize, "A" is the primary UUT which is instantiated in B and B is instantiated in C_tb. 

A has generics, but B and C_tb have no generics. 

 

As you guess there is no problem with the functional simulation, but once I try to run the post-synthesis simulation, I get the following error: 

binding entity "A" does not have generic xxx. 

 

As I said, there is no generics in the top-level file in the simulation and let me point out that I've read the related threads. What I found there is having generic in the top-level testbench, which is not valid in my case. 

 

Thanks

Hamid

 

(I'm using Vivado 15.4.1 and Zynq-7000)

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1 Solution

Accepted Solutions
Moderator
Moderator
16,970 Views
Registered: ‎07-01-2015

Re: Generics in testbench

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Hi @ahmadian,

 

Adding to @dprasad's suggestion, you can do it by setting the properties of the file.

Please go through the following snapshot.

 

Thanks,
Arpan

Thanks,
Arpan
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4 Replies
Moderator
Moderator
8,879 Views
Registered: ‎07-01-2015

Re: Generics in testbench

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Hi @ahmadian,

 

In post-synthesis/post-implementation, the generic(constant) are deleted and usage of those generic are replaced with constant value. So the same testbench for behavioral simulation (with generics) won't be applicable for post-synth/post-impl simulation.

 

Thanks,
Arpan

Thanks,
Arpan
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Xilinx Employee
Xilinx Employee
8,878 Views
Registered: ‎09-13-2014

Re: Generics in testbench

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If I understand it correctly then you have following

 

C_tb --> B --> A

 

Where A is instantiated in B like 

 

B --> A generic map (XXXXX)

 

In post-synthesis, these generics will be replaced with constant value so there is no reference of generic in post-synth netlist of A hence ERROR.

 

Solution: Generally UUT which is going for synthesis should not have any generic override from simulation file but in your case, you are doing so from design file 'B.vhd'. As 'B' instantiated in your test bench, simply changing it from simulation only to simulation-synthesis will solve the issue. 

 

--dhiRAj

 

Moderator
Moderator
16,971 Views
Registered: ‎07-01-2015

Re: Generics in testbench

Jump to solution

Hi @ahmadian,

 

Adding to @dprasad's suggestion, you can do it by setting the properties of the file.

Please go through the following snapshot.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Observer ahmadian
Observer
8,840 Views
Registered: ‎05-03-2015

Re: Generics in testbench

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Dear all, 

 

Thanks for the prompt replies. 

I changed the intermediate entity (B) as you said and in addition to that, I had to move this file in the design sources, though I don't intend to use it in the design. This means, to be able to use generics, one cannot use an intermediate entity in the simulation sources, but that intermediate entity must be a real hardware wrapper which includes the UUT. 

 

Thanks for your valuable hints and helps,

Hamid

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