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Visitor
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Registered: ‎05-12-2019

Get the real clock time in simulation - get_clocktime

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Hi,

Is there a way to get the real time clock in a VHDL test bench in Vivado?

In ModelSIM I'm using the modelsim_lib library that comes with get_clocktime, which allows for things like:

signal mti_sim : mti_clocktime_rec := get_clocktime(-1, TRUE);

constant file_name : string := "sim_log_" & integer'image(mti_sim.year) & "-" & integer'image(mti_sim.month) & "-" &
                               integer'image(mti_sim.day) & "_" & integer'image(mti_sim.hour) & "h" &
                               integer'image(mti_sim.minute) & "m" & integer'image(mti_sim.second) & "s.log";

/F

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Get the real clock time in simulation - get_clocktime

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VHDL has no standard way of getting the system time.

Modelsim have provided a library that allows this (probably via system hooks) but this is proprietary to modelsim. Other vendors may also provide their own libraries for this (I doubt Xilinx does) but it will be not be compatible with other tools.

VHDL 2019 does provide a standardised mechanism for this, but 3rd party tools from Aldec and Mentor are only just starting to support this standard. Xilinx still provides little simulation support for VHDL 2008, so dont expected VHDL 2019 support anytime soon.

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Visitor
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Registered: ‎05-12-2019

Re: Get the real clock time in simulation - get_clocktime

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Anyone? How do I get the wall clock time in the Vivado simulator?

Or am I forced to use SystemVerilog and try to get that into the VHDL test bench?

void'($system("date +%X--%x > sys_time"));

/F

EDIT: Seems like $system isn't supported.

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Scholar
Scholar
126 Views
Registered: ‎08-01-2012

Re: Get the real clock time in simulation - get_clocktime

Jump to solution

VHDL has no standard way of getting the system time.

Modelsim have provided a library that allows this (probably via system hooks) but this is proprietary to modelsim. Other vendors may also provide their own libraries for this (I doubt Xilinx does) but it will be not be compatible with other tools.

VHDL 2019 does provide a standardised mechanism for this, but 3rd party tools from Aldec and Mentor are only just starting to support this standard. Xilinx still provides little simulation support for VHDL 2008, so dont expected VHDL 2019 support anytime soon.

View solution in original post

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Visitor
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Registered: ‎05-12-2019

Re: Get the real clock time in simulation - get_clocktime

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Thanks for answering. Yes, I was thinking about a Xilinx provided library similar to the modelsim_lib.

And I've been painfully aware of the poor VHDL 2008 support in Vivado...

After digging deeper, the only way to get the wall clock time seems to be a TCL script (https://stackoverflow.com/questions/18141851/compile-date-and-time-in-fpga). Then using the xsim.compile.tcl.pre setting in Vivado to run the TCL script before launching the simulation. Or to use a completely scripted simulation.

/F

 

 

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