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581 Views
Registered: ‎07-29-2019

Getting wrong result in post implementation timing simulation

I have implemented a design in Ultra96 Evaluation Platform (XCZU3EG-SBVA484-1-E). Design is meeting timing constrain properly during implementation.

But during post implementation timing simulation I am getting the following warnings and getting wrong results.

WARNING: "C:\Xilinx\Vivado\2018.2\data/verilog/src/unisims/FDRE.v" Line 156: Timing violation in scope /tb_top_module/uut/uut8/x/u3/tanhreg_reg[22]/TChk156_3614 at time 11974508 ps $width (negedge R &&& init_enable,(0:0:0),0,notifier).

 

I verified all other simulations : Behavioral, post synthesys functional and timing, post implementation functional simulations, all are producing perfect result.

Only post implementation timing  simulation producing wrong results.

What should I do? Its very urgent please response.

 

 

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15 Replies
566 Views
Registered: ‎01-22-2015

Re: Getting wrong result in post implementation timing simulation

pkniitkgp@gmail.com 

Chapter 5 of the Ultrafast Design Methodology Guide, UG949, gives the Xilinx recommendations for achieving timing closure, which do not include running/passing post implementation timing simulation (PITS).

I suspect that the warning you received has to do with using PITS and not with your design.  Investigation of the warning  can be postponed until things are not so urgent for you.

Mark

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Scholar watari
Scholar
552 Views
Registered: ‎06-16-2013

Re: Getting wrong result in post implementation timing simulation

Hi pkniitkgp@gmail.com 

 

Did you make sure reset timing and reset pulse in your timing report file ?

It seems reset pulse issue.

 

Best regards,

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544 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

I have downloaded the bit stream in the ultra96 board and got wrong result.

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526 Views
Registered: ‎01-22-2015

Re: Getting wrong result in post implementation timing simulation

pkniitkgp@gmail.com 

  1. Check your assumptions #1: Are you sure the design is passing functional simulation?
  2. Check your assumptions #2: Are you sure the design is passing implementation/timing-analysis?  As watari suggests, don’t just look at WNS.  Also check WHS, WPWS, and all parts of the report generated by check_timing for problems.
  3. Check that the design is properly constrained: That is, follow recommendation starting on page 207 of UG949(v2019.1).  Generate the other suggested reports (eg. report_timing_summary, report_methodology, report_drc) and look for problems.

If none of the above show problems, then you may have written timing exceptions/constraints that you should not have written - which are allowing the design to pass timing analysis (when the design actually does not pass timing analysis).  Thus, you may need to return to "Baselining Your Design" as described on page 211 of UG949.  Baselining is a process in which you create the simplest timing constraints and initially ignore I/O timing.  Then, carefully add the timing exceptions/constraints needed to achieve timing closure.

Mark

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477 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

In systhesis I have created clock for 20 ns time period.

 

After synthesys I got timing summry like

WNS : inf, TNS: 0 ns

//------------------------

WHS: inf, THS: 0

//----------------------------

 

WPWS: NA, TPWS : NA

//--------

After Implementation I got timing summry like

WNS : 4.934ns, TNS: 0

//------------------------

WHS: 0.026ns, THS: 0

//----------------------------

 

WPWS: 4.725ns, TPWS : 0

 

The reports are ok.

 

 

 

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467 Views
Registered: ‎01-22-2015

Re: Getting wrong result in post implementation timing simulation

pkniitkgp@gmail.com 

The synthesis timing results are only approximate.  

The implementation timing results are most important.  If all the numbers you have shown are positive then implementation thinks your design passes timing analysis.  

However, since your design is not working on the board then the design may not actually pass timing analysis.  That is, perhaps  you have written timing constraints that are covering up timing analysis problems.

I suggest that you review all timing constraints and timing exceptions that you have written for your project. Ensure that each is needed and that each is written correctly.  

-or, as described by "Baselining the Design", starting on page 211 of UG949, start over with your constraints.  That is, start with a blank constraints file.  Then, add constraints slowly.  Begin by adding simply physical constraints and work your way towards adding the more complicated timing constraints.  Make sure that you understand each constraint and that each constraint is actually needed.

-on the other hand, a clock with 20ns period is a slow clock (for FPGAs).  Is this the only clock in your design?  We usually do not have timing analysis problems with such slow clocks.  Are you sure that you are passing functional simulation?

Mark

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459 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

I have started with baseline constrain and clock frequency is 50MHz

I found that the

In systhesis timing report are as follows

WNS 16.448 ns, TNS 0.0 ns

WHS : (-0.059 ns), THS (-11.180 ns) (violating)

WPWS 9.468 ns, TPWS 0.000 ns

//---------------------------------

But in implementation report I got perfect results as follows

WNS 15.618 ns, TNS 0.0 ns

WHS : 0.024 ns, THS 0.0 ns

WPWS 9.468 ns, TPWS 0.000 ns

Due to the violation in THS in synthesys report this problem is arising?

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450 Views
Registered: ‎01-22-2015

Re: Getting wrong result in post implementation timing simulation

    Due to the violation in THS in synthesys report this problem is arising?
No. Only the results from implementation timing analysis matter.

Some questions for you:

1) The Zynq (XCZU3EG-SBVA484-1-E) you are using has a PS-side and a PL-side.  Timing analysis results tell you only that PL-side things are working properly.  If you have written code for PS-side, how do you know it is working properly?

2) Please tell us all you can about your project and about why you think it is not working.

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434 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

My design passed the baselining timing constraints. All timing results are perfect.

I have done all the simulations: Behavioural, synthesis- function and timing, implementation-function and timing.

  Behavioural, synthesis- function and timing, implementation-function: all are giving perfect result.

In Implementation - timing simulation I am getting the following warning! (Operating frequency is 50 MHz)

WARNING: "C:\Xilinx\Vivado\2018.2\data/verilog/src/unisims/FDRE.v" Line 158: Timing violation in scope /tb_top_module/uut/uut8/x/u3/tanhreg_reg[11]/TChk158_3616 at time 934346 ps $width (posedge R &&& init_enable,(0:0:0),0,notifier)

and found results are deviating from functional simulation.

My questions are:

1. If my design meets implementation timing analysys (WNS,TNS,WHS,THS, TPWS) and implementation functional simulation. Should the design work on Board?? Or exact output of Implementation timing simulation is mandatory to get perfect result in board??

2. How can I resolve this worning and why implementation timing simulation results deviates from functional simulation?? Plz help.

 

 

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389 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

Please clarify my doubts...

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Xilinx Employee
Xilinx Employee
378 Views
Registered: ‎07-16-2008

Re: Getting wrong result in post implementation timing simulation

With regards to the warning itself, it looks the width timing check of reset pin (FDRE.R) is violated.

WARNING: "C:\Xilinx\Vivado\2018.2\data/verilog/src/unisims/FDRE.v" Line 158: Timing violation in scope /tb_top_module/uut/uut8/x/u3/tanhreg_reg[11]/TChk158_3616 at time 934346 ps $width (posedge R &&& init_enable,(0:0:0),0,notifier)

You may want to open .sdf and search for the register in question. See how WIDTH for R pin is specified and cross check its positive pulse width at simulation time 934346 ps.

The WIDTH entry specifies limits for a minimum pulse width timing check. The minimum pulse width timing check is the minimum allowable time for the positive (high) or negative (low) phase of each cycle.

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349 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

Though my Post implementation timing results are deviating from the expected results, I am getting exact results after downloading in the FPGA. There is no discrepancy between expected results and FPGA's output.

Thank you all for your kind response.

In my design only Reset is the external input which I am giving from test bench. Reset is synchronous and active low. I am making the Reset low for three clock cycles, then also the following warning is comming and getting wrong post implemntation timing simulation (PITS) results.

WARNING: "C:\Xilinx\Vivado\2018.2\data/verilog/src/unisims/FDRE.v" Line 158: Timing violation in scope /tb_top_module/uut/uut8/x/u3/tanhreg_reg[11]/TChk158_3616 at time 934346 ps $width (posedge R &&& init_enable,(0:0:0),0,notifier)

I shall be highly obliged if you can suggest a proper solution for this wirning and get exact PITS.

 

 

 

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Highlighted
344 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

I have discussed with my friends who are using VIVADO tools. They are also getting wrong PITS data. But after downlad the design giving exact result.

I hope simulation tools have some problems. Please share your experiences.

Thanks.

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327 Views
Registered: ‎01-22-2015

Re: Getting wrong result in post implementation timing simulation

If the error you are seeing is associated with the external reset for your project, then try using XPM_CDC_ASYNC_RST as described on page 9 of UG974 (v2019.1).

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322 Views
Registered: ‎07-29-2019

Re: Getting wrong result in post implementation timing simulation

my reset is synchronous. Is it useful?

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