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Visitor
Visitor
9,363 Views
Registered: ‎01-06-2015

HDL simulation works, post synthesis simulation doesnt

Dear all,

 

I'm currently trying to use a statemachine to configure the clock IC on the VC709 eval board. The code is written in VHDL and has been implemented last year on a Spartan 6 and was tested successfully/worked in the hardware. I wrote a small testbench, supplying clock and reset signals, the rest comes from a small design with a I2C master component and a statemachine, that selects the registers to write.

When I run a behavioural simulation, the output is as expected. Data is written on the outputs and the statemachine finishes with a flag set high.

When I now synthesize the design and run a post synthesis functional simulation, I can see, that input data is created by the testbench correctly, but my statemachine is stuck even before the first data is send. I can also see different internal signals, that are marked red and with an X to show different driver forcing against each other, e.g. on a counter.

 

I have never encountered such a big difference between HDL synthesis and synth/implementation result. The HDL hasn't been altered but now synthesized for a different FPGA and with newer tools. Can anyone point me in the right direction on how to debug this problem? I'm not quite sure where to start, since synthesis-tools are blackbox for me with not much to influence.

 

Best Regards,

Björn

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4 Replies
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Moderator
Moderator
9,355 Views
Registered: ‎01-16-2013

Hi,

First step to debug this is to look into synthesis log. Check for warnings and critical warnings carefully.

Thanks,
Yash
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Moderator
Moderator
9,349 Views
Registered: ‎07-21-2014

Hi,

 

You can compare the generated log from both synthesis runs and also check generated messages.

 

Thanks,
Anusheel
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Xilinx Employee
Xilinx Employee
9,345 Views
Registered: ‎10-24-2013

Hi,
Looks like some FSM optimization related thing.
Try -flatten_hierarchy none in synthesis setting and see if that helps.
Also try using different options to -fsm_extraction and check if you are getting the expected output.

Check http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf for details on the above switches.
Thanks,Vijay
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Visitor
Visitor
9,328 Views
Registered: ‎01-06-2015

Hi,

 

I checked the synth messages and there is no critical warning. There are 24 normal warnings about unused signals, which have been removed (unused RX related registers, since the FSM only writes data, and a not connected warning, since I have still the port in the top sheet, but doesn't use it in this reduced design). I can't identify a problem with these optimizations.

 

I also deactivated the flatten_hierarchy feature and tried every option of the -fsm_extraction, without any changes in the simulation behavior, without any effect on the outcome.

 

Any further ideas? I will read into ug901 to see, if any other options may be more convincing.

 

Best Regards,

Björn

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