UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor mrnkhk
Visitor
13,301 Views
Registered: ‎08-14-2014

HDLCompiler:251 - Cannot access memory directly Error

Jump to solution

Hi all,
I'm giving a 2d array to a VHDL module.This 2d array is valued in a verilog module. The error that ISE is giving is that the 2d array is assumed a memory and can not be accessed. I've googled the error but there were no answers to this specific case. Please help me on this.
Here's the definition of the 2d array.

wire [IN_FIFO_DEPTH_BIT:0]  depth_of_fifo[NUM_QUEUES-1:0];//storing the depth of all FIFOs  
wire [IN_FIFO_DEPTH_BIT - 1:0] packet_size_temp[NUM_QUEUES-1:0];

Here's the part of my verilog code that is the source of the error.

Deficit_Round_Robbin_algorithem
#(
.Quantom(),
.Num_queues(NUM_QUEUES),
.IN_FIFO_DEPTH_BIT(IN_FIFO_DEPTH_BIT)
 )
algorithem_module(
.clk(axi_aclk),
.axi_resetn(axi_resetn),
.m_axis_tready(m_axis_tready),
.packet_size(packet_size_temp),  //Line 247
.fifo_out_tlast(fifo_out_tlast),
.empty(empty),
.rd_en(rd_en),
.pkt_fwd(pkt_fwd)
 );

And here is the error message

ERROR:HDLCompiler:251 - "K:/final project/codes/v3/input_arbiter.v" Line 247: Cannot access memory packet_size_temp directly
ERROR:HDLCompiler:598 - "K:/final project/codes/v3/input_arbiter.v" Line 46: Module <input_arbiter> ignored due to previous errors.

My complete verilog code and the vhdl module is in the attachment.

Thank you for your time and best regards!!

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Visitor mrnkhk
Visitor
23,774 Views
Registered: ‎08-14-2014

Re: HDLCompiler:251 - Cannot access memory directly Error

Jump to solution

Thanks for your answer morgan.

with some serious searching in popular forums eventually I found the answer.

The problem is with verilog! When ise or other tools synthesis a 2d array in verilog they think its a memory with address bits and data bits.

So if you want to access it you have to access it sequentially by defining 2 arrays one for the address one for the data,or for asynchronous access put the whole data bits in one big array or for every address define a seperate array.

For myself since i hade only 4 addresses i went with the last soloution and defined 4 arrays with the width of the data.

View solution in original post

0 Kudos
3 Replies
Voyager
Voyager
13,283 Views
Registered: ‎04-21-2014

Re: HDLCompiler:251 - Cannot access memory directly Error

Jump to solution

With this type of coding, I'd stick to either pure verilog or pure VHDL.  Your VHDL has some fairly advanced features, but it could be better organized. 

 

Check your dimmensions of packet_size in your VHDL and your Verilog.

 

If you're coding the VHDL, some training will get your code so that it is easier to review/maintain.  You're doing well, but it could be organized a lot better.

 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
Visitor mrnkhk
Visitor
23,775 Views
Registered: ‎08-14-2014

Re: HDLCompiler:251 - Cannot access memory directly Error

Jump to solution

Thanks for your answer morgan.

with some serious searching in popular forums eventually I found the answer.

The problem is with verilog! When ise or other tools synthesis a 2d array in verilog they think its a memory with address bits and data bits.

So if you want to access it you have to access it sequentially by defining 2 arrays one for the address one for the data,or for asynchronous access put the whole data bits in one big array or for every address define a seperate array.

For myself since i hade only 4 addresses i went with the last soloution and defined 4 arrays with the width of the data.

View solution in original post

0 Kudos
Voyager
Voyager
13,269 Views
Registered: ‎04-21-2014

Re: HDLCompiler:251 - Cannot access memory directly Error

Jump to solution

Good to hear, @mrnkhk

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
0 Kudos