Heat Generation from XCZU270R

[frank.odonnell1]

I have been trying to run a thermal anyalsis using the UltraScale+ as my chipset, however my simulation (nastran) is asking for the heat generation of the chip itself (w/m^3) which I cant find anywhere. I assumed the chip at maximum is outputing 35W and the size of the chip at 0.00000576 m^3, but the output doesnt make sense to me. If anyone could tell me what I am doing wrong that would be a great head start.

Thanks

[lowearthorbit]

The area should be the package area, times two,

In a properly designed heat sinking solution, half the power is from the top heat spreader (lid) of the packageout through heatsink/fan and half through the solder balls on the bottom of the package, out through the pcb itself.

l.e.o.

[archangel-lightworks]

@frank.odonnell1 

I assume by 'chip' you mean the package you can see on the PCB. It is wrong to assume there is an average heat generation within the whole package. The heat is generated in the silicon die, that is much smaller. A fraction of that goes to the heat spreader and another goes to the balls and PCB as @lowearthorbit  points. There is a number of different materials and conductivities inside the package so it's not easy to get a satisfactory thermal model. More than in this forum, I would look at FEM forums. Chip packages are more or less the same, independent of the manufacturer, so looking for things like what's inside a BGA could help. Finally, bear in mind the implications of modelling sub-mm regions, badly defined regions like the solder balls volumes and the space between package and PCB, plus the PCB with its copper planes having a significant impact, so every PCB needs a simulation. Is it really worth?

[drjohnsmith · Accepted solution]

Im assuming yo umean the XCZU27DR, not the 270

have you seen this

https://www.xilinx.com/support/documentation/application_notes/xapp1301-mechanical-thermal-design-guidelines.pdf

https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf

Different FPGA packages have different arangments of where the silicon is in the packages ( near top or bottom of the package ) and have different termal resistances ( deg C / watt ) to the lid and to the pins.

You will see in the second link theta JB ( junction to base )  and theta JC ( junction to case ),

The firs link shows you how hot you are allowed to run the silicon before it is out of specification , and ultimatly dead.

BTW: Where did yu get that watts your disipating,

   These ultrascale+ chips can dispate 200 Watts,

[frank.odonnell1]

This got me closer to what I needed, but Ill have to mess around this software some more.

Thanks