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gaochaoant
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Registered: ‎08-18-2008

Help!About Independent Clocks Block RAM

Hi!

 

I use ISE10.1,Modelsim 6.4c.I use Core Generator to generate FIFO.But I found that when I generated the common clock fifo,it is OK.But I use the Independent Clocks(RD_CLK,WR_CLK) fifo ,it is wrong.The Modelsim indicated "Component instance "buff : fifo48x4096" is not bound." Meanwhile the output is U,I can not get the simulation result.

 

Thank you!

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