02-06-2018 10:40 AM - edited 02-09-2018 07:13 PM
I need to design register file that is connected to an ALU in systemverilog,
then simulate the top module to verify that operations are performed correctly.
I attached three modules, alu, register file, top module.
I have verified that the alu itself works by running simulation independently from the register file.
Yet, when I run simulation for the top module I get dont care for the first bit of the result.
So the result gets loaded in the register file via WD (write data port) when EN is high.
Then what is A3.
Can someone explain more about register file.
02-09-2018 03:34 AM
I must say that I don't understand your question. Could you give more detail about what you are looking for?
What do you mean by " what to use for the output of the topalu module". Do you mean the data type?
02-12-2018 01:30 AM
Please do not change your initial question, else the following replies can make no sense. If you need to add more information, reply to the topic.
I still do not understand what you are looking for...
You designed a register file but you are asking about it...
02-12-2018 01:36 AM
I am having trouble in getting the result out when I do simulation. I input two numbers but I get don't care for the output.
02-12-2018 01:43 AM
I guess this is because you are not initializing your memory before reading it. So the simulator tells you the value outputted can be any value
02-12-2018 02:33 AM
I tried to do simulation for the register file alone. It works only when I have A1 A2 A3 = to same number, the output will follow whatever is in WD.
Can you help understand what I am doing wrong.
02-12-2018 02:50 AM
If A1 A2 A3 = to same number, then you are initializing the memory (with A3) and reading back this value (with A2 and A1)