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Visitor fadia
Visitor
1,632 Views
Registered: ‎10-04-2017

Help in simulating ALU

Hello,

I need to design register file that is connected to an ALU in systemverilog,

then simulate the top module to verify that operations are performed correctly.

I attached three modules, alu, register file, top module.
I have verified that the alu itself works by running simulation independently from the register file.
Yet, when I run simulation for the top module I get dont care for the first bit of the result.

So the result gets loaded in the register file via WD (write data port) when EN is high.

Then what is A3.

 

Can someone explain more about register file.

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7 Replies
Moderator
Moderator
1,570 Views
Registered: ‎11-09-2015

Re: Help in simulating ALU

Hi @fadia,

 

I must say that I don't understand your question. Could you give more detail about what you are looking for?

 

What do you mean by " what to use for the output of the topalu module". Do you mean the data type?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor fadia
Visitor
1,558 Views
Registered: ‎10-04-2017

Re: Help in simulating ALU

Thanks for your reply, I rewrote my question.

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Moderator
Moderator
1,523 Views
Registered: ‎11-09-2015

Re: Help in simulating ALU

Hi @fadia,

 

Please do not change your initial question, else the following replies can make no sense. If you need to add more information, reply to the topic.

 

I still do not understand what you are looking for...

 

You designed a register file but you are asking about it...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor fadia
Visitor
1,519 Views
Registered: ‎10-04-2017

Re: Help in simulating ALU

I am having trouble in getting the result out when I do simulation. I input two numbers but I get don't care for the output.

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Moderator
Moderator
1,512 Views
Registered: ‎11-09-2015

Re: Help in simulating ALU

Hi @fadia,

 

I guess this is because you are not initializing your memory before reading it. So the simulator tells you the value outputted can be any value


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor fadia
Visitor
1,507 Views
Registered: ‎10-04-2017

Re: Help in simulating ALU

I tried to do simulation for the register file alone. It works only when I have A1 A2 A3 = to same number, the output will follow whatever is in WD.

 

Can you help understand what I am doing wrong.

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Moderator
Moderator
1,501 Views
Registered: ‎11-09-2015

Re: Help in simulating ALU

Hi @fadia,

 

If A1 A2 A3 = to same number, then you are initializing the memory (with A3) and reading back this value (with A2 and A1)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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