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Visitor oclabbao
Visitor
411 Views
Registered: ‎02-05-2017

Help on generating Zynq7 IBIS model in Vivado

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Hello,

I am using Vivado 2017.4 for a XC7Z010 system with DDR3L SDRAM. I configured DDR Configuration for "DDR3 (Low voltage)" and memory part as "MT41K256*" which is a DDR3L chip.

When I generate IBIS model from "Export IBIS Model" from the implemented design and using the appropriate *.pkg and base zynq7.ibs, the generated IBIS model shows "SSTL15", instead of "SSTL135" which is what I was expecting. Is this OK, or have I missed a setting somewhere?

Thanks!

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Xilinx Employee
Xilinx Employee
397 Views
Registered: ‎08-25-2010

回复: Help on generating Zynq7 IBIS model in Vivado

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Hi @oclabbao,

Please ensure ddr3(low voltage) is selected in 2017.4. It might be modified to DDR3 after you running auto connection, and you need to select once more, then you can export the expected sstl135.

 

Thanks

Simon

Thanks
Simon
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Xilinx Employee
Xilinx Employee
398 Views
Registered: ‎08-25-2010

回复: Help on generating Zynq7 IBIS model in Vivado

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Hi @oclabbao,

Please ensure ddr3(low voltage) is selected in 2017.4. It might be modified to DDR3 after you running auto connection, and you need to select once more, then you can export the expected sstl135.

 

Thanks

Simon

Thanks
Simon
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Xilinx Employee
Xilinx Employee
396 Views
Registered: ‎08-10-2008

回复: Help on generating Zynq7 IBIS model in Vivado

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Hi o,

Sometimes if one IOstandard have exactly the same Model with another one, this can happen. For this, you will find lines in the .ibs file saying that the two types of pins are mapped to one same model.

Open the generated ibs file and check if this is the case. 

Besides, we provide a complete ibis model at https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/zynq-7000-ap-soc.html. I check this one but I don't find SSTL15 mapped to SSTL135 or vice verse. You need to provide the whole Model name for this  checking, like "SSTL135_DCI_F_PSDDR_IN50_I" because there are so many models.

If you cannot find such mapping, there may be something wrong with your xdc file. You can provide more details to debug.

 

Ivy

 

 

 

 

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Visitor oclabbao
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Registered: ‎02-05-2017

回复: Help on generating Zynq7 IBIS model in Vivado

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Thanks Simon.

I'll try to reimplement and see if that changes the output. I'll give an update on how it goes.

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Visitor oclabbao
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Registered: ‎02-05-2017

回复: Help on generating Zynq7 IBIS model in Vivado

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Thanks Ivy.

Yes I got the base IBIS files from that link. I'll double check the xdc, but if I remember correctly, there's currently no entry there for the SDRAM pins (mapping is fixed anyway, only the user assigned pins are there) and I let the system handle it. I'll try to add DDR3 mapping, see if that helps.

I'll keep you posted. Thanks!

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Visitor oclabbao
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Registered: ‎02-05-2017

回复: Help on generating Zynq7 IBIS model in Vivado

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Hi Simon. Ivy,

I did a "reset runs" and re-synthesized/implemented the design (making sure DDR3 low voltage is selected), and I got the SSTL135. Somehow, the DDR3 config did get modifed and now it's ok.

Thanks!

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