02-08-2018 07:34 AM
Hello, I am trying to simulate my design and I get this error. The design is a mixture of VHDL and Verilog. I get the following error when trying to simulate.
[XSIM 43-3253] File C:/Program Files/Opal Kelly/FrontPanelUSB/FrontPanelHDL/XEM7010-A50/okCoreHarness.v, line 9964. Verilog alias ports are not supported in mixed language simulation.
What is this referring to?
02-08-2018 07:41 AM
Refer the below link for restriction of Mixed language with Vivado simulator:
02-14-2018 03:09 AM
There is a list of what is supported in Mixed Language Simulation in Appendix G of User Guide 900 (attached).