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arquer
Explorer
Explorer
2,886 Views
Registered: ‎03-23-2015

HiZ assignment somehow prevaling over 1'b1 assignment

Hello,

 

I have an interface where I have packet some code to simulate the interface's master/slave (like a BFM). Inside the interface depending on how the user configures the interface, I assign the master/slave driven signals to the ones writen by the interfaces tasks.

 

If the user is not using the master/slave BFM code I assign a bunch of signals to HiZ, so that the interface itself won't drive any value onto them.

My surprise is that if I then assign an actual value to that signal from outside the interface with an "assign" statement, the statements since to have no effect, and the signal remains in HiZ. Shouldn't HiZ "lose" over some other assignment?

 

You can test the following code

 

interface MyInterface (
    input Clk, input Rst_n 
    );
    
    logic SomeSignal;
    assign SomeSignal = 'z;
    
endinterface


module myTb ();

    logic Clk = 0;
    logic Rst_n = 0;
    
    always #5 Clk = !Clk;
    
    initial begin
        Rst_n = 0;
        repeat (20) @(posedge Clk);
        Rst_n = 1;
    end
    
    MyInterface myInterface (.Clk(Clk), .Rst_n(Rst_n));
    
    assign myInterface.SomeSignal = 1;
    
endmodule

Here the interface is assigning the signal to 'z, but then I am assigning the same signal to 1 from the TB. If you look at the simulation results you will se the signal "SomeSignal" remains at HiZ...

 

I have found two ways to work around with which I don't like:

1. assign a value to myInterface.SomeSignal from a procedural block. I don't like this because it makes things harder when you just want to assign a constant or some other signal to it.

 

2. Change the interface definition and turn SomeSignal into a wire.I don't like this because a module which has such interface as a port can not directly drive the interface signals from a procedural statement. Instead the module would have to create auxiliary signals, set/clear those from a procedural block and then assign those auxiliary signals to the interface's signals with an "assign" statement.

 

Is this normal behavior? Am I just aking too much? or is there some way to achieve what I want?

 

Thanks!

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4 Replies
hpoetzl
Voyager
Voyager
2,878 Views
Registered: ‎06-24-2013

Unfortunately UG901 lists hierarchical names as unsupported in Verilog and "limited to interface and properties" for System Verilog. It's not much different for the VHDL support btw. which still has issues with hierarchical names.

 

Hope that helps,

Herbert

-------------- Yes, I do this for fun!
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shameera
Moderator
Moderator
2,869 Views
Registered: ‎05-31-2017

Hi @arquer,

As, @hpoetzl suggested  hirerchical reference to any interface port is not supported by Vivado.

Please check the below linked AR#55135 for unsupported System Verilog constructs.

https://www.xilinx.com/support/answers/55135.html

 

Thanks & Regards,

A.Shameer.

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arquer
Explorer
Explorer
2,859 Views
Registered: ‎03-23-2015

Thanks for the reply @hpoetzl @shameera,

 

could it be that the support for this kind of hierarchical references works if I do the assignment (wether continuous or procedural) from a sub-module?

 

I am using this interface to connect other blocks and I had not found this issue until now (when I tried to reference it from the top level module). My signals are defined as logic as I showed and I have blocks which function correctly which both perform continuous assignments with "assign" as well as procedural assignments...

 

So if you try the following code:

interface MyInterface (
    input Clk, input Rst_n 
    );
    
    logic SomeSignal;
    logic SomeOtherSignal;
    assign SomeSignal = 'z;
    assign SomeOtherSignal = 'z;
endinterface

module mySubModule (
    input logic Clk,
    input logic Rst_n,
    MyInterface myInterface
    );
    
    assign myInterface.SomeSignal = Clk;
    
    always @(posedge Clk) begin
        if (!Rst_n)
            myInterface.SomeOtherSignal <= 1'b0;
        else
            myInterface.SomeOtherSignal <= !myInterface.SomeOtherSignal;
    end
       
endmodule

module myTb ();

    logic Clk = 0;
    logic Rst_n = 0;
    
    always #5 Clk = !Clk;
    
    initial begin
        Rst_n = 0;
        repeat (20) @(posedge Clk);
        Rst_n = 1;
    end
    
    MyInterface myInterface (.Clk(Clk), .Rst_n(Rst_n));
    
    mySubModule SUBMODULE_I (
        .Clk(Clk),
        .Rst_n(Rst_n),
        .myInterface(myInterface)
    );

endmodule
    
    

You will see how the signals are assigned fine...

So if this is really an unsupported feature, which I found weird because accessing hierarchical names inside an interface seems to be supported, just not from the top-level module, is there any plan to support it soon?

 

EDIT: Also forgot to mention, the list of unsupported features listed in that link is for synthesis aparently.. all this is during simulation. I am using Vivado 2017.2 btw.

 

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hpoetzl
Voyager
Voyager
2,838 Views
Registered: ‎06-24-2013

Unfortunately simulation is even further behind on language support than synthesis.

For example, most VHDL 2008 constructs are not supported at all, even if they are working in synthesis.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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