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vivian07593
Visitor
Visitor
530 Views
Registered: ‎03-21-2019

High impendence in signed register

I decleared the input and register were signed. 

When posedge clk, let the input data send to signed register. But the higher bits are high impedence, lower bits have value.

I think is the signed register didn't get the sign extension that verilog did.

How to solve this problem?

 

input signed [25:0] ecg_in;
register signed [25:0] V5_1;

always@(posedge clk)
begin
         if(count<5)
              V5_1 <= ecg_in;
end 

擷取.PNG 

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timothyv
Xilinx Employee
Xilinx Employee
485 Views
Registered: ‎07-11-2019

Hello @vivian07593 

I was wondering if you could provide more information on your problem, such as the entirety of the source code and the testbench module? Those sources would help in debugging your simulation output. If you could also provide the version of Vivado that you are using, that would be helpful. 

 

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